clarify primer

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index a2fc94f0c4633c2fc0ad711031adac0befd4184f..99fcd8b591a15c2abd33fffb44b7bf724183e0de 100644 (file)
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -110,6 +110,9 @@ the number of instructions increase:
        \item Documentation of the ISA
        \item Manual coding and optimisation
        \item Time to support the platform
+       \item Compilance Suite development and testing
+    \item Protracted Variable-Length encoding (x86) severely compromises
+          Multi-issue decoding
 \end{itemize}
 
 \subsection{Simple Vectorisation}
@@ -124,9 +127,9 @@ Main design principles
 \begin{itemize}
        \item Introduce by implementing on top of existing Power ISA
        \item Effectively a \textbf{hardware for-loop}, pauses main PC,
-             issues multiple scalar op's
-       \item Preserves underlying scalar execution dependencies as
-             the for-loop had been expanded as actual scalar instructions
+             issues multiple scalar operations
+       \item Preserves underlying scalar execution dependencies as if
+             the for-loop had been expanded into actual scalar instructions
         ("preserving Program Order")
        \item Augments existing instructions by adding "tags" - provides
           Vectorisation "context" rather than adding new opcodes.
@@ -135,7 +138,8 @@ Main design principles
           advantage in the vector space (see \ref{subsubsec:add_to_pow_isa})
        \item Aimed at Supercomputing: avoids creating significant
              \textit{sequential dependency hazards}, allowing \textbf{high
-             performance superscalar microarchitectures} to be deployed.
+             performance multi-issue superscalar microarchitectures} to be
+          leveraged.
 \end{itemize}
 
 Advantages include: