remove clk from spi_flash,

change cs_n to cs,
de-bork WB access with stall=cyc&~ack thing

diff --git a/src/ls2.py b/src/ls2.py
index f16425b5665421c359d98c3f84a0f901f9309122..315224569c166ebb26ad3a83659140ece47fc00f 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -391,6 +391,8 @@ class DDR3SoC(SoC, Elaboratable):
         # SPI controller
         if spi_0_pins is not None and fpga in ['sim',
                                              'rcs_arctic_tern_bmc_card',
+                                             'versa_ecp5',
+                                             'versa_ecp5_85',
                                              'arty_a7']:
             # The Lattice ECP5 devices require special handling on the
             # dedicated SPI clock line, which is shared with the internal
@@ -409,13 +411,13 @@ class DDR3SoC(SoC, Elaboratable):
             # The main SPI Flash (SPI 1) should be set to at
             # least 28 bits (256MB) to allow the use of large 4BA devices.
             self.spi0 = Tercel(data_width=32, spi_region_addr_width=24,
+                               features={'stall'},
                                clk_freq=clk_freq,
                                pins=spi_0_pins,
                                lattice_ecp5_usrmclk=spi0_is_lattice_ecp5_clk)
             self._decoder.add(self.spi0.bus, addr=spi0_addr)
             self._decoder.add(self.spi0.cfg_bus, addr=spi0_cfg_addr)
 
-
         # Ethernet MAC
         if ethmac_0_pins is not None and fpga in ['versa_ecp5',
                                                   'versa_ecp5_85',
@@ -530,6 +532,12 @@ class DDR3SoC(SoC, Elaboratable):
         self.uart.add_verilog_source(fname, platform)
 
         if hasattr(self, "spi0"):
+            # add spi submodule
+            m.submodules.spi0 = spi = self.spi0
+            # gonna drive me nuts, this.
+            comb += spi.bus.stall.eq(spi.bus.cyc & ~spi.bus.ack)
+            comb += spi.cfg_bus.stall.eq(spi.cfg_bus.cyc & ~spi.cfg_bus.ack)
+
             # add Tercel verilog source. assumes a directory structure where
             # microwatt has been checked out in a common subdirectory with:
             # git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi
@@ -661,7 +669,9 @@ def build_platform(fpga, firmware):
     # Get SPI resource pins
     spi_0_pins = None
     if platform is not None and fpga in ['rcs_arctic_tern_bmc_card',
-                                         'arty_a7']:
+                                         'arty_a7',
+                                         'versa_ecp5_85',
+                                         'versa_ecp5']:
         # XXX naming-conventions for nmigen_boards/resources/interface.py
         # SPIResource are "spi" not "spi_0", and for SPIFlashResources
         # the name convention is "spi_flash_1x" (or 2x or 4x)
@@ -669,17 +679,18 @@ def build_platform(fpga, firmware):
             # The ECP5 series FPGAs handle the SPI clock directly on
             # the FPGA configuration Flash device
             spi_0_pins = platform.request("spi_flash_4x", 0,
-                                        dir={"dq":"io", "cs_n":"o"},
-                                        xdr={"dq": 1, "cs_n": 1})
+                                        dir={"dq":"io", "cs":"o"},
+                                        xdr={"dq": 1, "cs": 1})
         else:
             spi_0_pins = platform.request("spi_flash_4x", 0,
-                                        dir={"dq":"io", "cs_n":"o", "clk":"o"},
-                                        xdr={"dq": 1, "cs_n": 1, "clk": 0})
+                                        dir={"dq":"io", "cs":"o", "clk":"o"},
+                                        xdr={"dq": 1, "cs": 1, "clk": 0})
     print ("spiflash pins", spi_0_pins)
 
     # Get Ethernet RMII resource pins
     ethmac_0_pins = None
-    if platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
+    if False and platform is not None and \
+       fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # TODO, like this, which needs a patch to nmigen_boards
         # from nmigen_boards.resources.interfaces import RMIIResource
         # hyperram_ios = RMIIResource(0, cs_n="V12 V14 U12 U14",