(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 7193a586b8a0611a59292ab62d0d23e9c1e956e2..fe4b8a3fd71cc63ae14cf74796117eca2001f604 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -468,8 +468,9 @@ only the bottom 32 bits (numbered 32:63 in MSB0 numbering).
 *Programmer's note: using `sv.mfcr` without element-width overrides
 to take into account the fact that the top 32 MSBs are zero and thus
 effectively doubling the number of GPR registers required to hold all 128
-CR Fields would seem the only option because normally elwidth overrides
-would halve the capacity of the instruction.  However in this case it
+CR Fields would seem the only option because a source elwidth override
+to 32-bit would take only the bottom 16 LSBs of the Condition Register
+and set the top 16 LSBs to zeros.  However in this case it
 is possible to use destination element-width overrides (for `sv.mfcr`.
 source overrides would be used on the GPR of `sv.mtocrf`), whereupon
 truncation of the 64-bit Condition Register(s) occurs, throwing away