add sys_rst to Clock Reset Generator

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index ef7d44512b653b2141c7c0fb007f5a758d92ec92..660760e6fde5e803fa96da2678f7d7af622f599c 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -129,7 +129,8 @@ class LibreSoCSim(SoCCore):
             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
         # CRG -----------------------------------------------------------------
-        self.submodules.crg = CRG(platform.request("sys_clk"))
+        self.submodules.crg = CRG(platform.request("sys_clk"),
+                                  platform.request("sys_rst"))
 
         #ram_init = []