(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index eabb471b1527400e38bd439c9c5b1c634f7c5560..92521b0ec4a15fc1fa4ceb66d6696f18b0cc6909 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -70,7 +70,7 @@ alternative table definition for [[sv/svp64]] `RM.MODE`.  The following
 modes make sense:
 
 * saturation
-* predicate-result (mostly for cache-inhibited LD/ST)
+* predicate-result would be useful but is lower priority than Data-Dependent Fail-First
 * simple (no augmentation)
 * fail-first (where Vector Indexed is banned)
 * Signed Effective Address computation (Vector Indexed only)
@@ -82,8 +82,7 @@ of space, have the following quirks:
 
 * LD/ST Immediate has no individual control over src/dest zeroing,
   whereas LD/ST Indexed does.
-* LD/ST Indexed has limited zeroing on pred-result, LD/ST Immediate has
-  *no* option to select zeroing on pred-result.
+* LD/ST Immediate has saturation but LD/ST Indexed does not.
 
 ## Format and fields
 
@@ -104,6 +103,12 @@ Fields used in tables below:
   EA is stored in RA **after** it is actually used.
 * **LF** - Load/Store Fail or Fault First: for any reason Load or Store Vectors
   may be truncated to (at least) one element, and VL altered to indicate such.
+* **VLi* - Inclusive Data-Dependent Fail-First: the failing element is included
+  in the Truncated Vector.
+
+When VLi=0 on Store Operations the Memory update does **not** take place
+on the element that failed.  EA does **not** update into RA on Load/Store
+with Update instructions either.
 
 **LD/ST immediate**
 
@@ -456,10 +461,17 @@ when VLi is clear, must all pass the "test", but when VLi is set the
 update (store) to Memory is **not permitted to take place** should the
 test fail. Therefore, on testing the value to be stored, and after updating
 the corresponding CR Field Element, when VLi=0 and finding that the
-test fails the Memory store must **not** occur.  By contrast if VLi=1
-and the test the Store may proceed *and then* looping terminates.
+test fails the Memory store must **not** occur.
+
+Additionally, when VLi=0 and a test fails then RA does **not** receive a
+copy of the Effective Address.  Hardware implementations with Out-of-Order
+Micro-Architectures should use speculative Shadow-Hold and Cancellation
+when the test fails.
+
+By contrast if VLi=1
+and the test fails, Store may proceed *and then* looping terminates.
 In this way, when non-Inclusive, the Vector of Truncated results contains
-only Stores that passed the test, and when Inclusive the Vector of
+only Stores that passed the test (and RA=EA updates if any), and when Inclusive the Vector of
 Truncated results contains the first-failed data.
 
 Below is an example of loading the starting addresses of Linked-List nodes.