Reduce wishbone address size to 32-bit

For now ... it reduces the routing pressure on the FPGA

This needs manual adjustment of the address decoder in soc.vhdl, at
least until I can figure out how to deal with std_match

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
# Conflicts:
#	soc.vhdl

# Conflicts:
#	soc.vhdl

diff --git a/soc.vhdl b/soc.vhdl
index 94ab39366c5e68942f22a12a6b76f8a6c2c760c1..458a751511d1048c0315df43bfcad12b79320e2b 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -111,11 +111,11 @@ begin
                            SLAVE_NONE);
        variable slave : slave_type;
     begin
-       -- Simple address decoder
+       -- Simple address decoder.
        slave := SLAVE_NONE;
-       if wb_master_out.adr(63 downto 24) = x"0000000000" then
+       if wb_master_out.adr(31 downto 24) = x"00" then
            slave := SLAVE_MEMORY;
-       elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
+       elsif wb_master_out.adr(31 downto 24) = x"c0" then
            if wb_master_out.adr(23 downto 12) = x"002" then
                slave := SLAVE_UART_0;
            end if;

diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl
index 928424426b0a8e352bddcf2fe0e85b6e08cff9be..12f0bc7902c59187de903c9f320bb0a414201225 100644 (file)
--- a/wishbone_types.vhdl
+++ b/wishbone_types.vhdl
@@ -2,7 +2,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 package wishbone_types is
-    constant wishbone_addr_bits : integer := 64;
+    constant wishbone_addr_bits : integer := 32;
     constant wishbone_data_bits : integer := 64;
     constant wishbone_sel_bits : integer := wishbone_data_bits/8;