add reduced instruction list

diff --git a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
index 3d8b0ef3aedba156d43d863b46f24b756085943f..3b63343a3245c2c1076ce11df35e407de22f1063 100644 (file)
--- a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
+++ b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
@@ -1,8 +1,45 @@
 [[!tag standards]]
 
-Attempt at reducing the number of different instructions used for int/fp moves.
+Attempt at [reducing the number of different instructions](#reduced-instruction-list) used for int/fp moves.
 IMPORTANT: don't merge until everyone's had a chance to review it.
 
+## tables for reduced instruction list
+
+| S_AND_RC | PowerISA naming scheme |
+|----------|------------------------|
+| 0        | `fmvtg`                |
+| 1        | `fmvtg.`               |
+| 2        | `fmvtgs`               |
+| 3        | `fmvtgs.`              |
+
+| INT_MODE | PowerISA naming scheme | Integer Type    |
+|----------|------------------------|-----------------|
+| 0        | `fcvtfgw[s][.]`        | signed 32-bit   |
+| 1        | `fcvtfguw[s][.]`       | unsigned 32-bit |
+| 2        | `fcvtfgd[s][.]`        | signed 64-bit   |
+| 3        | `fcvtfgud[s][.]`       | unsigned 64-bit |
+
+## reduced instruction list <a name="reduced-instruction-list"></a>
+
+| old                                  | new                                        | notes                               |
+|--------------------------------------|--------------------------------------------|-------------------------------------|
+| `fmvis FRS, D`                       | `fmvis FRS, D`                             | submitted to ISA WG so don't modify |
+| `fishmv FRS, D`                      | `fishmv FRS, D`                            | submitted to ISA WG so don't modify |
+| `fmvtg[s][.] RT, FRA`                | `fmvtg RT, FRA, S_AND_RC`                  | goes against PowerISA naming scheme |
+| `fmvfg[s][.] FRT, RA`                | `fmvfg FRT, RA, S_AND_RC`                  | goes against PowerISA naming scheme |
+| `fcvtfg[u][w/d][s][.] FRT, RA`       | `fcvtfg FRT, RA, S_AND_RC, INT_MODE`       | goes against PowerISA naming scheme |
+| `fcvt[s]tg[u][w/d][.] RT, FRA, Mode` | `fcvttg RT, FRA, Mode, S_AND_RC, INT_MODE` | goes against PowerISA naming scheme |
+
+Notes:
+* PowerISA uses `s` and `.` suffixes instead of an immediate for Single and Rc=1 modes respectively.
+* PowerISA uses `w`, `uw`, `d`, and `ud` suffixes instead of an immediate for selecting between unsigned/signed 32-bit/64-bit.
+
+About the only operations we can realistically remove are Rc=1 versions, however imho that isn't necessary.
+
+Realistically we can't remove any of the Rc=0 instructions because it would make the instruction set non-orthogonal and it would penalize the code using those operations, almost all of which are quite common.
+
+Attempting to condense them into 6 instructions by undoing the PowerISA naming scheme works, but all that changed is the assembler mnemonics (in a bad way by being inconsistent with PowerISA), the instruction encodings don't change at all, unless we want to use an expanded opcode.
+
 # Rest of document not yet modified:
 
 # FPR-to-GPR and GPR-to-FPR