rename ls180 litex pll_48 output to pll_18

diff --git a/libreriscv b/libreriscv
index 0dbab7b582bdcf7e75aadff81551abec621d81f2..6c32e64727c7030a7c672620b281b4f3a9076ffd 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 0dbab7b582bdcf7e75aadff81551abec621d81f2
+Subproject commit 6c32e64727c7030a7c672620b281b4f3a9076ffd

diff --git a/pinmux b/pinmux
index 8145bb58bc29bd642e6c9a3653b942783e6a3e87..7f8cbf72abced671b4d0d1ae358d656470220ca4 160000 (submodule)
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 8145bb58bc29bd642e6c9a3653b942783e6a3e87
+Subproject commit 7f8cbf72abced671b4d0d1ae358d656470220ca4

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 370f9cdc2fb30cf518d48a87d3d066cbbb4eb28e..b01c5fc8a7811db043d47b6e6a061d88ba107bd6 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -239,10 +239,10 @@ class LibreSoC(CPU):
 
         # add clock select, pll output
         if variant == "ls180":
-            self.pll_48_o = Signal()
+            self.pll_18_o = Signal()
             self.clk_sel = Signal(3)
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
-            self.cpu_params['o_pll_48_o'] = self.pll_48_o
+            self.cpu_params['o_pll_18_o'] = self.pll_18_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index c47cbea5c8d3d1eb50d029dc66db81d8900c9efe..f8580d37a35ea6783f5d33e7e1e729917eac91e0 100644 (file)
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -50,7 +50,7 @@ def io():
         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
-        ("sys_pll_48_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
+        ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
 
         # JTAG0: 4 pins
         ("jtag", 0,

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 4279effcffe2fbf15f877e9b2a1b76beab248dac..52c83ea40a60e65d422857ba845f7e54b76268c2 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -365,10 +365,10 @@ class LibreSoCSim(SoCCore):
 
         # PLL/Clock Select
         clksel_i = platform.request("sys_clksel_i")
-        pll48_o = platform.request("sys_pll_48_o")
+        pll18_o = platform.request("sys_pll_18_o")
 
         self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-        self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL
+        self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
 
         #ram_init = []