(no commit message)

diff --git a/3d_gpu/architecture/inorder_model.mdwn b/3d_gpu/architecture/inorder_model.mdwn
index b0679dc0c2f720c25a860d47cc1bea28a417d9c9..7f25c35be33779058a2009b3056711d4151598d5 100644 (file)
--- a/3d_gpu/architecture/inorder_model.mdwn
+++ b/3d_gpu/architecture/inorder_model.mdwn
@@ -15,7 +15,7 @@ A Single-Issue In-Order control unit will allow every pipepline to be active,
 and raises the ideal maximum throughput to 1 instruction per clock cycle,
 bearing any register hazards.
 
-This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/), however there's currently a
+This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/ and there are options in the Makefile to enable it), however there's currently a
 task to develop the model for the simulator first. The model will be used to
 determine performance.