hmmm XICS data being asserted on wb bus for too long

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index 23e966470c50e5d45b64559d3b40e76abb658632..a0a852d3bd6ad61eb74634e3289743c0a0d6f133 100644 (file)
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -93,8 +93,9 @@ class XICS_ICP(Elaboratable):
         # We delay core_irq_out by a cycle to help with timing
         sync += self.core_irq_o.eq(r.irq)
 
-        comb += self.bus.dat_r.eq(r.wb_rd_data)
-        comb += self.bus.ack.eq(r.wb_ack)
+        comb += self.bus.ack.eq(r.wb_ack & self.bus.cyc)
+        with m.If(self.bus.ack):
+            comb += self.bus.dat_r.eq(r.wb_rd_data)
 
         v = RegInternal()
         xirr_accept_rd = Signal()