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update FPGA connector images
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 4 Nov 2020 15:26:35 +0000 (15:26 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 4 Nov 2020 15:26:45 +0000 (15:26 +0000)
HDL_workflow/2020-11-03_13-22.png patch | blob | history
HDL_workflow/versa_ecp5_x3_connector.jpg patch | blob | history

diff --git a/HDL_workflow/2020-11-03_13-22.png b/HDL_workflow/2020-11-03_13-22.png
index 1eb99708e2389f9565dd8599f1a8a190bce7e4e6..ac3732f697935277e13a28739d305aa280c09023 100644 (file)
Binary files a/HDL_workflow/2020-11-03_13-22.png and b/HDL_workflow/2020-11-03_13-22.png differ
diff --git a/HDL_workflow/versa_ecp5_x3_connector.jpg b/HDL_workflow/versa_ecp5_x3_connector.jpg
index 992fe9f744143fe6121686d4e70909a6d5434f0b..e0ada75ad8c666d2a59ce98447ab0d7c884b8b06 100644 (file)
Binary files a/HDL_workflow/versa_ecp5_x3_connector.jpg and b/HDL_workflow/versa_ecp5_x3_connector.jpg differ
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