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revise diagram to include twin-l0-port
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 27 Apr 2020 10:34:32 +0000 (11:34 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 27 Apr 2020 10:34:32 +0000 (11:34 +0100)
3d_gpu/180nm_single_core_testasic_memlayout.jpg patch | blob | history

diff --git a/3d_gpu/180nm_single_core_testasic_memlayout.jpg b/3d_gpu/180nm_single_core_testasic_memlayout.jpg
index 7d957c2a33551ccf5e993a2f8f29dcf029e4631b..03c39a852c459b218ca8c1aeca3e1259bbe38661 100644 (file)
Binary files a/3d_gpu/180nm_single_core_testasic_memlayout.jpg and b/3d_gpu/180nm_single_core_testasic_memlayout.jpg differ
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