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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 98d2adac845ebb01c13930a40b092ffd85925bba..426b2130e469f0af6515babe62e40b92d6aa80a6 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -49,7 +49,7 @@ However programmers can reconfigure the register file data types, if the default
 | v30                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
 
-Both Andes Packed SIMD and Harmonised RVP are intended to be "low end" SIMD implementations for processors without dedicated vector registers.
+Both Andes Packed SIMD and Harmonised RVP are intended to be "low end" SIMD implementations (for processors without dedicated vector registers).
 Instead, the integer register file is used for SIMD operations.  To maintain forwards compatibility with "high end" RV Vector implementations, programmer should use VLD and VST to load/store vectors.  The implementation will then load/store a vector to/from the register file supported by the implementation.
 
 To keep implementations simple and focused on within-register SIMD only, there is a strict 1:1 mapping between vectors (v0-v31) and integer registers (r0-r31).  Standard calling conventions apply and so callee saved integer registers should be saved before being used as vector registers.