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diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index d2747b2db4f14dbd27199c7d9e13a8dd5ecce3b2..d08308cc5986192fa0e4df40a43d561a8ea9dba8 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -486,15 +486,17 @@ zero in the predicate will be the NULL pointer*
    RA=0 # vec - first one is valid, contains ptr
    imm = 8 # offset_of(ptr->next)
    for i in range(VL):
+       # this part is the Scalar Defined Word (standard scalar ld operation)
        EA = GPR(RA+i) + imm          # ptr + offset(next)
        data = MEM(EA, 8)             # 64-bit address of ptr->next
        GPR(RT+i) = data              # happens to be read on next loop!
        # was a normal vector-ld up to this point. now the Data-Fail-First
-       CR.field(i) = conditions(data)
-       if CR.field(i).EQ == testbit: # check if zero
-           if VLI then   VL = i+1                   # update VL, inclusive
-           else          VL = i                     # update VL
-           break                     # stop looping
+       cr_test = conditions(data)
+       if Rc=1 or RC1: CR.field(i) = cr_test # only store if Rc=1/RC1
+       if cr_test.EQ == testbit:             # check if zero
+           if VLI then   VL = i+1            # update VL, inclusive
+           else          VL = i              # update VL, exclusive current
+           break                             # stop looping
 ```
 
 **Data-Dependent Fault-First on Store-Conditional (Rc=1)**
@@ -502,16 +504,18 @@ zero in the predicate will be the NULL pointer*
 There are very few instructions that allow Rc=1 for Load/Store:
 one of those is the `stdcx.` and other Atomic Store-Conditional
 instructions.  With Simple-V being a loop around Scalar instructions
-strictly obeying Scalar Program Order a Fail-First loop on an
-Atomic Store-Conditional will always fail the second and all other
-Store-Conditional instructions in Horizontal-First Mode because
+strictly obeying Scalar Program Order a Horizontal-First Fail-First loop
+on an Atomic Store-Conditional will always fail the second and all other
+Store-Conditional instructions because
 Load-Reservation and Store-Conditional are required to be executed
 in pairs.
 
 By contrast, in Vertical-First Mode it is in fact possible to issue
 the pairs, and consequently allowing Vectorised Data-Dependent Fail-First is
-useful.  Care should be taken however when VL is truncated in Vertical-First
-Mode.
+useful.
+
+Programmer's note: Care should be taken when VL is truncated in
+Vertical-First Mode.
 
 **Future potential**
 
@@ -519,8 +523,8 @@ Although Rc=1 on LD/ST is a rare occurrence at present, future versions
 of Power ISA *might* conceivably have Rc=1 LD/ST Scalar instructions, and
 with the SVP64 Vectorisation Prefixing being itself a RISC-paradigm that
 is itself fully-independent of the Scalar Suffix Defined Words, prohibiting
-Rc=1 Data-Dependent Mode on future potential LD/ST operations is not
-strategically sound.
+the possibility of Rc=1 Data-Dependent Mode on future potential LD/ST
+operations is not strategically sound.
 
 ## LOAD/STORE Elwidths <a name="elwidth"></a>