add instance
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 17 Jul 2018 07:54:57 +0000 (08:54 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 17 Jul 2018 07:54:57 +0000 (08:54 +0100)
src/bsv/bsv_lib/Makefile.pwm.templates
src/bsv/bsv_lib/pwm.bsv
src/bsv/bsv_lib/pwm_instance.bsv [new file with mode: 0644]

index 8794355b8a56460cda4a38fa3a04d1ab191a8d8d..fb08aa7aa42c4736934f85d3aff373569b4f4d1b 100644 (file)
@@ -1,7 +1,7 @@
 ### Makefile for the srio
 
-TOP_MODULE:=mkPWM_bus
-TOP_FILE:=pwm.bsv
+TOP_MODULE:=mkPWM_bus_real
+TOP_FILE:=pwm_instance.bsv
 HOMEDIR:=./
 TOP_DIR:=./
 BSVBUILDDIR:=./build/
index 42bcbdea238d71c5b90adb87bba7e67109c7814b..b760f814ef1eefbdc10e3cd191f271567fb49912 100644 (file)
@@ -65,7 +65,7 @@ package pwm;
   endinterface
 
   //(*synthesize*)
-  module mkPWM#(Clock ext_clock, numeric pwmnum_)(PWM);
+  module mkPWM#(Clock ext_clock, numeric type pwmnum_)(PWM);
 
     let pwmnum = valueOf(pwmnum_);
 
@@ -269,7 +269,7 @@ package pwm;
     endinterface
 
     //(*synthesize*)
-    module mkPWM_bus#(Clock ext_clock, numeric pwmnum)(Ifc_PWM_bus);
+    module mkPWM_bus#(Clock ext_clock, numeric type pwmnum)(Ifc_PWM_bus);
       PWM pwm <-mkPWM(ext_clock, pwmnum);
                AXI4_Lite_Slave_Xactor_IFC#(`PADDR,`Reg_width, `USERSPACE)
                                     s_xactor<-mkAXI4_Lite_Slave_Xactor();
diff --git a/src/bsv/bsv_lib/pwm_instance.bsv b/src/bsv/bsv_lib/pwm_instance.bsv
new file mode 100644 (file)
index 0000000..c543165
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+*  Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-------------------------------------------------------------------------------------------------
+
+Code inpired by the pwm module at: https://github.com/freecores/pwm
+
+*/
+package pwm_instance;
+  /*=== Project imports ==*/
+  import Clocks::*;
+  /*======================*/
+  /*== Package imports ==*/
+  //import defined_types::*;
+  `include "instance_defines.bsv"
+  import ClockDiv::*;
+  import ConcatReg::*;
+       import Semi_FIFOF::*;
+       import BUtils ::*;
+  `ifdef PWM_AXI4Lite
+       import AXI4_Lite_Types::*;
+  `endif
+    import pwm::*;
+  /*======================*/
+
+  `ifdef PWM_AXI4Lite
+    // the following interface and module will add the
+    // AXI4Lite interface to the PWM module
+    interface Ifc_PWM_bus_real;
+      interface Ifc_PWM_bus pwmbus;
+    endinterface
+
+    //(*synthesize*)
+    module mkPWM_real#(Clock ext_clock)(Ifc_PWM_bus);
+      Ifc_PWM_bus pwmbus <-mkPWM_bus(ext_clock, 32);
+      interface pwm_io = pwmbus.pwm_io.io;
+      interface axi4_slave = pwmbus.axi4_slave;
+    endmodule
+  `endif
+
+endpackage