whitespace

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index c70a7877a13a8ee728d537d637176002bd5ff2f3..48c63be0991dfc6547216fe6cb4a24e4d9b7bd58 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -246,7 +246,7 @@ REMAP is outlined separately.
   of the predicates provides all of the other types of operations
   found in Vector ISAs (VEXTRACT, VINSERT etc) again with no need
   to actually provide explicit such instructions.
-* **Saturation**. applies to **all** LD/ST and Arithmetic and Logical 
+* **Saturation**. applies to **all** LD/ST and Arithmetic and Logical
   operations (without adding explicit saturation ops)
 * **Reduction and Prefix-Sum** (Fibonnacci Series) Modes, including a
   "Reverse Gear" (running loops backwards).
@@ -262,7 +262,7 @@ REMAP is outlined separately.
   solve the "SIMD Considered Harmful" stripmining problem from a Memory
   Access perspective.
 * **Data-Dependent Fail-First**: a 100% Deterministic extension of the LDST
-  ffirst concept: first `Rc=1 BO test` failure terminates looping and 
+  ffirst concept: first `Rc=1 BO test` failure terminates looping and
   truncates VL to that exact point. Useful for implementing algorithms
   such as `strcpy` in around 14 high-performance Vector instructions, the
   option exists to include or exclude the failing element.
@@ -501,7 +501,7 @@ from inside Vertical-First Loops, and potentially allows arbitrarily-depth
 nested VF Loops.
 
 Simple-V Vertical-First Looping requires an explicit instruction to
-move `SVSTATE` regfile offsets forward: `svstep`. An early version of 
+move `SVSTATE` regfile offsets forward: `svstep`. An early version of
 Vectorised
 Branch-Conditional attempted to merge the functionality of `svstep`
 into `sv.bc`: it became CISC-like in its complexity and was quickly reverted.
@@ -790,7 +790,7 @@ that is as follows:
   allocated to Simple-V
 * all other patterns are `RESERVED` for other non-Vectoriseable
   purposes (just over 37.5%).
-  
+
 | 0-5 | 6 | 7 | 8-31  | 32:33 |  Description               |
 |-----|---|---|-------|-------|----------------------------|
 | PO9?| 0 | 0 | !zero | 00-10 | RESERVED (other)           |
@@ -973,7 +973,7 @@ OR:
 | 64bit | ss.fishmv | 0x24!zero    | 0x12345678| scalar SVP64Single:EXT2nn |
 | 64bit | sv.fishmv | 0x25nnnnnn   | 0x12345678| vector SVP64:EXT2nn |
 
-Here the encodings are the same, 0x12345678 means the same thing in 
+Here the encodings are the same, 0x12345678 means the same thing in
 all cases. Anything other than this risks either damage (truncation
 of capabilities of Simple-V) or far greater complexity in the
 Decode Phase.
@@ -982,7 +982,7 @@ This drives the compromise proposal (above) to reserve certain
 EXT2nn POs right
 across the board
 (in the Scalar Suffix side, irrespective of Prefix), some allocated
-to Simple-V, some not.  
+to Simple-V, some not.
 
 **illegal due to missing**
 
@@ -1058,7 +1058,7 @@ and:
 Both of these Simple-V operations are illegally-allocated. The fact that
 there does not exist a scalar "Defined Word" (even for EXT200-263) - the
 unallocated block - means that the instruction may **not** be allocated in
-the Simple-V space.  
+the Simple-V space.
 
 **illegal attempt to put Scalar EXT004 into Vector EXT2nn**