experiments9/freepdk_c4m45: Reduce core size.

With a core size of 1.5x1.5mm the effective space margin is 20%.

diff --git a/experiments9/freepdk_c4m45/doDesign.py b/experiments9/freepdk_c4m45/doDesign.py
index 87ada2f72c47b6fbf8df115722b080ab86022e58..1d31ca513564afbddf60fb0dce38e55ca6d3befd 100644 (file)
--- a/experiments9/freepdk_c4m45/doDesign.py
+++ b/experiments9/freepdk_c4m45/doDesign.py
@@ -135,9 +135,9 @@ def scriptMain (**kw):
    #helpers.setTraceLevel( 550 )
    #Breakpoint.setStopLevel( 100 )
     rvalue     = True
-    coreSize   = u(37*90.0)
-   #coreSize   = u(59*90.0)
-    chipBorder = u(2*214.0 + 10*13.0)
+    coreSize   = u(1500.0)
+    chipSize   = u(3400.0)
+    # chipBorder = u(2*214.0 + 10*13.0)
     ioSpecs    = IoSpecs()
     pinmuxFile = './ls180/litex_pinpads.json'
     ioSpecs.loadFromPinmux( pinmuxFile )
@@ -237,7 +237,8 @@ def scriptMain (**kw):
         ls180Conf.chipConf.name = 'chip'
         ls180Conf.chipConf.ioPadGauge = 'LibreSOCIO'
         ls180Conf.coreSize = (coreSize, coreSize)
-        ls180Conf.chipSize = (coreSize + chipBorder, coreSize + chipBorder)
+        # ls180Conf.chipSize = (coreSize + chipBorder, coreSize + chipBorder)
+        ls180Conf.chipSize = (chipSize, chipSize)
 
         with UpdateSession():
             sliceHeight = ls180Conf.sliceHeight