Somewhat working dynamic shifter
authorMichael Nolan <mtnolan2640@gmail.com>
Wed, 12 Feb 2020 16:22:18 +0000 (11:22 -0500)
committerMichael Nolan <mtnolan2640@gmail.com>
Wed, 12 Feb 2020 16:22:18 +0000 (11:22 -0500)
src/ieee754/part_shift_scalar/part_shift_dynamic.py
src/ieee754/part_shift_scalar/test/test_shift_dynamic.py

index d3bd0c08201db665dd93770c708f76c26e41e364..a32e5bfd5c5ac2eac4603708f89fb2ca4aa93f46 100644 (file)
@@ -31,7 +31,8 @@ class PartitionedDynamicShift(Elaboratable):
         m = Module()
         comb = m.d.comb
         width = self.width
-        gates = self.partition_points.as_sig()
+        gates = Signal(self.partition_points.get_max_partition_count(width)-1)
+        comb += gates.eq(self.partition_points.as_sig())
 
         matrix = []
         keys = list(self.partition_points.keys()) + [self.width]
@@ -40,9 +41,10 @@ class PartitionedDynamicShift(Elaboratable):
         for i in range(len(keys)):
             row = []
             start = 0
-            for i in range(len(keys)):
-                end = keys[i]
-                row.append(Signal(width - start))
+            for j in range(len(keys)):
+                end = keys[j]
+                row.append(Signal(width - start,
+                           name="matrix[%d][%d]" % (i, j)))
             matrix.append(row)
 
         a_intervals = []
@@ -70,12 +72,18 @@ class PartitionedDynamicShift(Elaboratable):
         for i in range(1, len(out_intervals)):
             index = gates[:i]  # selects the 'i' least significant bits
                                # of gates
-            for index in range(1<<(i-1)):
+            element = Signal(width, name="element%d" % i)
+            for index in range(1<<i):
+                print(index)
                 with m.Switch(gates[:i]):
                     with m.Case(index):
-                        element = matrix[index][i]
+                        index = math.ceil(math.log2(index + 1))
+                        comb += element.eq(matrix[index][i])
             print(keys[i-1])
-            intermed = Mux(gates[i-1], element, element | intermed[:keys[i-1]])
+            temp = Signal(width, name="intermed%d" % i)
+            print(intermed[keys[0]:])
+            intermed = Mux(gates[i-1], element, element | intermed[keys[0]:])
+            comb += temp.eq(intermed)
             comb += out_intervals[i].eq(intermed)
 
 
index 5e899992dd31d6e8bbd9a4688f0f1344c68920c3..ec60d7c6a95e8836e029e1acbca2c667c009f849 100644 (file)
@@ -46,12 +46,15 @@ class DynamicShiftTestCase(FHDLTestCase):
             yield a.eq(0x01010101)
             yield b.eq(0x04030201)
             for i in range(1<<(mwidth-1)):
-                yield gates.eq(0)
+                yield gates.eq(i)
                 yield Delay(1e-6)
                 yield Settle()
             yield gates.eq(1)
             yield Delay(1e-6)
             yield Settle()
+            yield gates.eq(0)
+            yield Delay(1e-6)
+            yield Settle()
 
 
         sim.add_process(process)