partial synthesize with EXTERNAL_CORE

diff --git a/Makefile b/Makefile
index fcc4258f5d82a013b26764b3b9c1045497afe1da..77c453f38c4ddca5824036339ff0c1b5ff27fe4c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -226,6 +226,15 @@ CLK_FREQUENCY=50000000
 clkgen=fpga/clk_gen_bypass.vhd
 endif
 
+FPGA_MAIN_BRAM=fpga/main_bram.vhdl
+
+_fpga_files = fpga/soc_reset.vhdl \
+       fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd $(FPGA_MAIN_BRAM) \
+       nonrandom.vhdl
+       
+_soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
+       wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
+       spi_rxtx.vhdl spi_flash_ctrl.vhdl
 
 
 #--
@@ -239,10 +248,11 @@ ifeq ($(EXTERNAL_CORE),false)
 
        synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 else
+#incomplete: does not build yet
     util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
-                core_dummy.vhdl
+                core_dummy.vhdl helpers.vhdl gpio.vhdl cache_ram.vhdl plru.vhdl
     fpga_files = $(_fpga_files) $(_soc_files)
-    synth_files = $(util_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+    synth_files = $(util_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
     soc_extra_v = external_core_top.v
 endif
 #--

diff --git a/core_dummy.vhdl b/core_dummy.vhdl
index 8967bb73c3687d493ecd9b9e80ae0a57854c4f38..8d944ef40b1676fea4fed352e19b8269183330bc 100644 (file)
--- a/core_dummy.vhdl
+++ b/core_dummy.vhdl
@@ -10,6 +10,17 @@ entity core is
     generic (
         SIM : boolean := false;
        DISABLE_FLATTEN : boolean := false;
+       
+       -- new in tplaten_3d_game
+       HAS_SHORT_MULT : boolean := false; 
+       ICACHE_NUM_LINES : natural := 64;
+    ICACHE_NUM_WAYS : natural := 2;
+    ICACHE_TLB_SIZE : natural := 64;
+    DCACHE_NUM_LINES : natural := 64;
+    DCACHE_NUM_WAYS : natural := 2;
+    DCACHE_TLB_SET_SIZE : natural := 64;
+    DCACHE_TLB_NUM_WAYS : natural := 2;
+        
         EX1_BYPASS : boolean := true;
         HAS_FPU : boolean := true;
         HAS_BTC : boolean := true;
@@ -30,6 +41,8 @@ entity core is
 
         wishbone_data_in  : in wishbone_slave_out;
         wishbone_data_out : out wishbone_master_out;
+        
+        wb_snoop_in     : in wishbone_master_out; -- new in tplaten_3d_game
 
        dmi_addr        : in std_ulogic_vector(3 downto 0);
        dmi_din         : in std_ulogic_vector(63 downto 0);