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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 1e6aba6521bd1537639fda5a71e47bb125200ed8..8df72f3674e57cce6cdee2448e0f8217c6e7c8a8 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -642,5 +642,19 @@ similar to x86 "rex" prefix.
 
 For actual assembler:
 
-    sv.asmcode.mode.vec reg.v/8, src.s/16, pred={maskreg}, spred={maskreg}
-
+    sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s
+
+For modes:
+
+* pred-result:
+  - pm=lt/gt/le/ge/eq/ne/so/ns OR
+  - pm=RC1 OR pm=~RC1
+* fail-first
+  - ff=lt/gt/le/ge/eq/ne/so/ns OR
+  - ff=RC1 OR pm=~RC1
+* saturation:
+  - sats
+  - satu
+* map-reduce:
+  - mr OR crm: "normal" map-reduce mode or CR-mode
+  - svm: when SUBVL=2/3/4 (vec2/3/4) sub-vector mapreduce is enabled