boards/arty: remove specific arty_symbiflow platform and adapt target to use standard...

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index 7f21fac80cca89f4f37ee9389163df8599f2a4a7..32059448745c5e7b6fa8f39d0eba50c3130fbbd9 100644 (file)
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -254,12 +254,12 @@ class Platform(XilinxPlatform):
     default_clk_name   = "clk100"
     default_clk_period = 1e9/100e6
 
-    def __init__(self, variant="a7-35"):
+    def __init__(self, variant="a7-35", toolchain="vivado"):
         device = {
             "a7-35":  "xc7a35ticsg324-1L",
             "a7-100": "xc7a100tcsg324-1"
         }[variant]
-        XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
+        XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
         self.toolchain.additional_commands = \

diff --git a/litex/boards/platforms/arty_symbiflow.py b/litex/boards/platforms/arty_symbiflow.py
deleted file mode 100644 (file)
index c931c34..0000000
--- a/litex/boards/platforms/arty_symbiflow.py
+++ /dev/null
@@ -1,35 +0,0 @@
-# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform
-from litex.build.openocd import OpenOCD
-from litex.boards.platforms.arty import _io, _connectors
-
-# Platform -----------------------------------------------------------------------------------------
-
-class Platform(XilinxPlatform):
-    default_clk_name   = "clk100"
-    default_clk_period = 1e9/100e6
-
-    def __init__(self, variant="a7-35"):
-        device = {
-            "a7-35":  {"part": "xc7a35tcsg324-1", "symbiflow-device": "xc7a50t_test"},
-        }[variant]
-        XilinxPlatform.__init__(self, device["part"], _io, _connectors, toolchain="symbiflow")
-        self.toolchain.symbiflow_device = device["symbiflow-device"]
-
-    def create_programmer(self):
-        bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
-        return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
-
-    def do_finalize(self, fragment):
-        # Prevent GenericPlatform from creating period constraint on input clock
-        pass
-
-    def add_period_constraint(self, clk, period, phase=0):
-        if clk is None: return
-        if hasattr(clk, "p"):
-            clk = clk.p
-        self.toolchain.add_period_constraint(self, clk, period, phase)

diff --git a/litex/boards/targets/arty_symbiflow.py b/litex/boards/targets/arty_symbiflow.py
index 0869b1ed3e1cc96845368b6de3d6b53373ddf4c3..394ffe722d17976494d7e8950137da7d60135d02 100755 (executable)
--- a/litex/boards/targets/arty_symbiflow.py
+++ b/litex/boards/targets/arty_symbiflow.py
@@ -9,7 +9,7 @@ import argparse
 
 from migen import *
 
-from litex.boards.platforms import arty_symbiflow
+from litex.boards.platforms import arty
 from litex.build.xilinx.symbiflow import symbiflow_build_args, symbiflow_build_argdict
 
 from litex.soc.cores.clock import *
@@ -22,10 +22,10 @@ from litex.soc.cores.led import LedChaser
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys       = ClockDomain()
+        self.clock_domains.cd_sys = ClockDomain()
 
         clk100_ibuf = Signal()
-        clk100_buf = Signal()
+        clk100_buf  = Signal()
         self.specials += Instance("IBUF", i_I=platform.request("clk100"), o_O=clk100_ibuf)
         self.specials += Instance("BUFG", i_I=clk100_ibuf, o_O=clk100_buf)
 
@@ -34,15 +34,15 @@ class _CRG(Module):
         pll.register_clkin(clk100_buf, 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
-        platform.add_period_constraint(clk100_buf, 1e9/100e6, 0)
-        platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq, 0)
+        platform.add_period_constraint(clk100_buf, 1e9/100e6)
+        platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
         platform.add_false_path_constraints(clk100_buf, self.cd_sys.clk)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(60e6), with_ethernet=False, with_etherbone=False, **kwargs):
-        platform = arty_symbiflow.Platform()
+        platform = arty.Platform(toolchain="symbiflow")
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)

diff --git a/test/test_targets.py b/test/test_targets.py
index ec767b15f29f3f8c747b692594aa76e67009d6ee..ddf2788bd0abb2505ba2dde6d3b4b88e3d8af765 100644 (file)
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -119,21 +119,21 @@ class TestTargets(unittest.TestCase):
     def test_simple(self):
         platforms = []
         # Xilinx
-        platforms += ["minispartan6"]                                                # Spartan6
-        platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", "arty_symbiflow"] # Artix7
-        platforms += ["kc705", "genesys2"]                                           # Kintex7
-        platforms += ["kcu105"]                                                      # Kintex Ultrascale
+        platforms += ["minispartan6"]                              # Spartan6
+        platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7
+        platforms += ["kc705", "genesys2"]                         # Kintex7
+        platforms += ["kcu105"]                                    # Kintex Ultrascale
 
         # Altera/Intel
-        platforms += ["de0nano"]                                                     # Cyclone4
+        platforms += ["de0nano"]                                   # Cyclone4
 
         # Lattice
-        platforms += ["tinyfpga_bx"]                                                 # iCE40
-        platforms += ["machxo3"]                                                     # MachXO3
-        platforms += ["versa_ecp5", "ulx3s"]                                         # ECP5
+        platforms += ["tinyfpga_bx"]                               # iCE40
+        platforms += ["machxo3"]                                   # MachXO3
+        platforms += ["versa_ecp5", "ulx3s"]                       # ECP5
 
         # Microsemi
-        platforms += ["avalanche"]                                                   # PolarFire
+        platforms += ["avalanche"]                                 # PolarFire
 
         for p in platforms:
             with self.subTest(platform=p):