add SVState SPR Record, SVSTATERec

diff --git a/src/soc/sv/svstate.py b/src/soc/sv/svstate.py
new file mode 100644 (file)
index 0000000..7307ce6
--- /dev/null
+++ b/src/soc/sv/svstate.py
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: LGPLv3+
+# Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Funded by NLnet http://nlnet.nl
+"""SVSATE SPR Record.  actually a peer of PC (CIA/NIA) and MSR
+
+https://libre-soc.org/openpower/sv/sprs/
+
+| Field | Name     | Description           |
+| ----- | -------- | --------------------- |
+| 0:6   | maxvl    | Max Vector Length     |
+| 7:13  |    vl    | Vector Length         |
+| 14:20 | srcstep  | for srcstep = 0..VL-1 |
+| 21:27 | dststep  | for dststep = 0..VL-1 |
+| 28:29 | subvl    | Sub-vector length     |
+| 30:31 | svstep   | for svstep = 0..SUBVL-1  |
+"""
+
+from nmigen import Record
+
+class SVSTATERec(Record):
+    def __init__(self, name=None):
+        Record.__init__([("maxvl"     : 8),
+                         ("vl"        : 7),
+                         ("srcstep"   : 7),
+                         ("dststep"   : 7),
+                         ("subvl"     : 2),
+                         ("svstep"    : 2), name=name)
+