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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index d7b6b5b14b28ab5f1621bbca525c3e37e0500d77..63fb9d500965dd2c2de2b7e6dd520d1942129c90 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -158,30 +158,26 @@ example.  For SVP64 there is insufficient space to make the SVP64 Prefix
 had to be individually analysed, by rote, to craft an EXTRA Field Mapping.
 This process was semi-automated and is described in this section.
 The final results, which are part of the SVP64 Specification, are here:
+[[openpower/opcode_regs_deduped]]
 
-* [[openpower/opcode_regs_deduped]]
-
-Firstly, every instruction's mnemonic (`add RT, RA, RB`) was analysed
+* Firstly, every instruction's mnemonic (`add RT, RA, RB`) was analysed
 from reading the markdown formatted version of the Scalar pseudocode
 which is machine-readable and found in [[openpower/isatables]].  The
 analysis gives, by instruction, a "Register Profile".  `add RT, RA, RB`
 for example is given a designation `RM-2R-1W` because it requires
 two GPR reads and one GPR write.
-
-Secondly, the total number of registers was added up (2R-1W is 3 registers)
+* Secondly, the total number of registers was added up (2R-1W is 3 registers)
 and if less than or equal to three then that instruction could be given an
 EXTRA3 designation.  Four or more is given an EXTRA2 designation because
 there are only 9 bits available.
-
-Thirdly, the instruction was analysed to see if Twin or Single
+* Thirdly, the instruction was analysed to see if Twin or Single
 Predication was suitable.  As a general rule this was if there
 was only a single operand and a single result (`extw` and LD/ST)
 however it was found that some 2 or 3 operand instructions also
 qualify. Given that 3 of the 9 bits of EXTRA had to be sacrificed for use
 in Twin Predication, some compromises were made, here.  LDST is
 Twin but also has 3 operands in some operations, so only EXTRA2 can be used.
-
-Fourthly, a packing format was decided: for 2R-1W an EXTRA3 indexing
+* Fourthly, a packing format was decided: for 2R-1W an EXTRA3 indexing
 could have been decided
 that RA would be indexed 0 (EXTRA bits 0-2), RB indexed 1 (EXTRA bits 3-5)
 and RT indexed 2 (EXTRA bits 6-8).  In some cases (LD/ST with update)
@@ -189,8 +185,7 @@ RA-as-a-source is given a **different** EXTRA index from RA-as-a-result
 (because it is possible to do, and perceived to be useful). Rc=1
 co-results (CR0, CR1) are always given the same EXTRA index as their
 main result (RT, FRT).
-
-Fifthly, in an automated process the results of the analysis
+* Fifthly, in an automated process the results of the analysis
 were outputted in CSV Format for use in machine-readable form
 by sv_analysis.py <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>