add a simple addis test (regression)

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index f1265a3a17cc5be272cd4ec2d464ee09da00ff14..51d4e7a182230f5ab091561d1c4c89e990f6a022 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -220,6 +220,13 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
+    def test_30_addis(self):
+        lst = [#"addi 0, 0, 5",
+               "addis 12, 0, 0",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [0, 12])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
         initial_regs = [0] * 32