sync changes from ls006 -> int_fp_mv

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index fe5a549efcc7edc88568046030e82254eace0898..becbd7e5fa22f7e671ee7dba8b8edbaad5c38db7 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -305,7 +305,11 @@ operations.
 
 Special Registers altered:
 
+```
     CR0     (if Rc=1)
+```
+
+----------
 
 ## Floating Move To GPR Single
 
@@ -331,9 +335,15 @@ operations.
 
 Special Registers altered:
 
+```
     CR0     (if Rc=1)
+```
 
-## Floating Move From GPR
+----------
+
+\newpage{}
+
+## Double-Precision Floating Move From GPR
 
 ```
     fmvfg FRT, RB
@@ -357,7 +367,11 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
+```
+
+----------
 
 ## Floating Move From GPR Single
 
@@ -383,7 +397,9 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
+```
 
 # Conversions
 
@@ -392,7 +408,7 @@ these instructions perform conversions between Integer and
 Floating Point. Truncation can therefore occur, as well
 as exceptions.
 
-## Floating Convert From Integer In GPR
+## Double-Precision Floating Convert From Integer In GPR
 
 ```
     fcvtfg FRT, RB, IT
@@ -451,8 +467,10 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
     FPCSR   (TODO: which bits?) (if IT[0]=1)
+```
 
 ### Assembly Aliases
 
@@ -510,8 +528,10 @@ operations.
 
 Special Registers altered:
 
+```
     CR1     (if Rc=1)
     FPCSR   (TODO: which bits?)
+```
 
 ### Assembly Aliases
 
@@ -626,8 +646,7 @@ Power ISA v3.1B):
 
 <div id="fp-to-int-java-saturating-conversion-semantics"></div>
 [Java/Saturating conversion semantics](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
-(only for long/int results)/
-[Rust semantics](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
+(only for long/int results)
 (with adjustment to add non-truncate rounding modes):
 
 ```
@@ -656,7 +675,7 @@ Section 7.1 of the ECMAScript / JavaScript
         return (int)bits
 ```
 
-## Floating Convert To Integer In GPR
+## Double-Precision Floating Convert To Integer In GPR
 
 ```
     fcvttg RT, FRB, CVM, IT
@@ -784,9 +803,11 @@ that overflow.
 
 Special Registers altered:
 
+```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
     FPCSR   (TODO: which bits?)
+```
 
 ### Assembly Aliases
 
@@ -930,9 +951,11 @@ that overflow.
 
 Special Registers altered:
 
+```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
     FPCSR   (TODO: which bits?)
+```
 
 ### Assembly Aliases