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missing self.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 1 May 2021 12:22:30 +0000 (13:22 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 1 May 2021 12:22:30 +0000 (13:22 +0100)
src/soc/experiment/l0_cache.py patch | blob | history

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 43bee1e9f299655be746065a8dfc50f0e7d14fb5..8414f77f75631691df9c358646fac454de950040 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -326,7 +326,7 @@ class TstL0CacheBuffer(Elaboratable):
 
         # really bad hack, the LoadStore1 classes already have the
         # lsi (LoadStoreInterface) as a submodule.
-        if pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
+        if self.pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
             return m
 
         # hmmm not happy about this - should not be digging down and