when an exception happens, if it is a fetch_failed take the

exception from the MMU not from LDST.

at some point need a much more sophisticated way of detecting which
unit created which exception

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3d285baabcd17d51b5a89640c2e8a342888d09fa..6f822726bb73327f402ec6540ddcec4ef22dbeac 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -892,7 +892,14 @@ class TestIssuerInternal(Elaboratable):
                     # nothing else needs to be done other than to note
                     # the change of PC and MSR (and, later, SVSTATE)
                     with m.If(exc_happened):
-                        sync += pdecode2.ldst_exc.eq(core.fus.get_exc("ldst0"))
+                        mmu = core.fus.get_exc("mmu0")
+                        ldst = core.fus.get_exc("ldst0")
+                        with m.If(fetch_failed):
+                            # instruction fetch: exception is from MMU
+                            sync += pdecode2.ldst_exc.eq(mmu)
+                        with m.Else():
+                            # otherwise assume it was a LDST exception
+                            sync += pdecode2.ldst_exc.eq(ldst)
 
                     with m.If(exec_pc_o_valid):