noted that major/minor opcodes can be used in 16-bit C immediates

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 3cc2ed562773eaf8344667315883f9309b41ea05..17c372ce2be6fd76333b50b1aad6849c255239bc 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -89,20 +89,23 @@ The Compressed Major Opcode is in bits 5-7.
 
 only available in 16-bit mode, and only available when M=1 and N=1
 
-    | 0 | 1  | 2 3 4 | | 567.8 | 9ab  | c d e     | f |
-    | 1 | o2 |  RT   | | 010.1 | RB|0 | offs      | addi.
-    | 1 | o2 |  RT   | | 011.1 | RB|0 | offs      | addis.
-    | 1 | o2     | 0 | | 100.1 | RB   | offs      | cmpdi
-    | 1 | o2     | 1 | | 100.1 | RB   | offs      | cmpwi
-    | 1 | o2     | 0 | | 101.1 | RA   | offs      | ldi
-    | 1 | o2     | 1 | | 101.1 | RA   | offs      | lwi
-    | 1 | o2     | 0 | | 110.1 | RA   | offs      | flwi
-    | 1 | o2     | 1 | | 110.1 | RA   | offs      | fldi
+    | 0 | 1  | 2 3 4 | | 567.8 | 9ab  | c d e | f |
+    | 1 | o2 |  RT   | | 010.0 | RB|0 | offs  | 1 | addi.
+    | 1 | o2 |  RT   | | 010.1 | RB|0 | offs  | 1 | addis.
+    | 1 | o2         | | 011.0 | RB   | offs  | 1 | cmpdi
+    | 1 | o2         | | 011.1 | RB   | offs  | 1 | cmpwi
+    | 1 | o2         | | 100.0 | RT   | offs  | 1 | sti
+    | 1 | o2         | | 100.1 | RT   | offs  | 1 | fstwi
+    | 1 | o2         | | 101.0 | RA   | offs  | 1 | ldi
+    | 1 | o2         | | 101.1 | RA   | offs  | 1 | lwi
+    | 1 | o2         | | 110.0 | RA   | offs  | 1 | flwi
+    | 1 | o2         | | 110.1 | RA   | offs  | 1 | fldi
 
 * Note that bc is included (below)
 * immediate is constructed from offs (LSBs) and o2 (MSB)
-* for loads, offset is aligned.  8byte: o2||offs||0b000 4byte: 0b00
-* RB|0 if RB is zero, addi. becomes "li"
+* for LD/ST, offset is aligned.  8-byte: o2||offs||0b000 4-byte: 0b00
+* RB|0 if RB is zero, addi. becomes "li" (this only works if RT takes
+  part of opcode).
 
 ### Branch