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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index be125bde41f769198165fb5f0cc66df16a6a726b..a7e53d90deb24d3c2b3c1abe41a30a25d064262f 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -196,6 +196,16 @@ for example), which
 will force implementations to perform divide and modulo
 calculations.
 
+An additional caveat involves Condition Register Fields
+when also used as Predicate Masks. An operation that
+overwrites the same CR Fields that are simultaneously
+being used as a Predicate Mask is `UNDEFINED` behaviour.
+This allows implementations to relax some of the
+otherwise-draconian Register Hazards that would otherwise
+occur, and to consider internal cacheing of the CR-based
+Predicate
+bits. 
+
 ## Register files, elements, and Element-width Overrides
 
 The relationship between register files, elements, and element-width