Fix autopep8 madness

diff --git a/contrib/simulation b/contrib/simulation
new file mode 100644 (file)
index 0000000..83f1922
--- /dev/null
+++ b/contrib/simulation
@@ -0,0 +1,2 @@
+cd gram/simulation
+time ./runsimcrg.sh
\ No newline at end of file

diff --git a/gram/dfii.py b/gram/dfii.py
index 34d85bc3ca100411f7c7b1208542547f367f80f3..53053fe42a791c986a410549d81dbcea77954ba1 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -61,12 +61,9 @@ class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
         self._nranks = nranks
 
-        self._inti = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
-        self.slave = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
-        self.master = dfi.Interface(
-            addressbits, bankbits, nranks, databits, nphases)
+        self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
 
         self._control = csr_bank.csr(4, "w")  # sel, cke, odt, reset_n