(no commit message)

diff --git a/simple_v_extension/vector_ops.mdwn b/simple_v_extension/vector_ops.mdwn
index 4d93ab2ed06e99fd7439dceddd46df9cf5f695f9..9d16c7593ab4436cf381f854c2047e23e192defb 100644 (file)
--- a/simple_v_extension/vector_ops.mdwn
+++ b/simple_v_extension/vector_ops.mdwn
@@ -317,3 +317,9 @@ Another is to overwrite one of the src registers.
 # Opcode Table
 
 TODO
+
+# Links
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002736.html>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002733.html>
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=142>