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Formal proof of the phased write dual port memory wrapper
authorCesar Strauss <cestrauss@gmail.com>
Sun, 3 Apr 2022 18:24:16 +0000 (15:24 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 3 Apr 2022 18:27:51 +0000 (15:27 -0300)
Similar to the proof of the 1RW memory block, but read and writes are
done on dedicated ports.
For now, only transparent regfile is tested.
To complete the formal verification, an induction proof will follow.


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