add comment on sv.setvl

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 7c200b215abd3e6f6e19e75d85d30fa49fdecad5..eced4438ff86f3d962663660c11769bfeb5adbdb 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -108,3 +108,7 @@ It leaves space for future expansion to RV128 and/or multi-register predicates.
         // rd is not x0
         regs[rd] = vl
     }
+
+# links
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001881.html>