add gt part_sig operator

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 4930ff0afdcf0a203a5e6ed55436eeed6623b101..4740e68e2f6cc0f680bbf67aed2c64ab2f34f61b 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -38,7 +38,7 @@ class PartitionedSignal:
         width = self.sig.shape()[0] # get signal width
         self.partpoints = make_partition(mask, width) # create partition points
         self.modnames = {}
-        for name in ['add', 'eq']:
+        for name in ['add', 'eq', 'gt']:
             self.modnames[name] = 0
 
     def set_module(self, m):
@@ -82,7 +82,6 @@ class PartitionedSignal:
         return pa.output
 
     def __eq__(self, other):
-        print ("eq", self, other)
         shape = self.sig.shape()
         pa = PartitionedEqGtGe(shape[0], self.partpoints)
         setattr(self.m.submodules, self.get_modname('eq'), pa)
@@ -94,3 +93,17 @@ class PartitionedSignal:
         else:
             comb += pa.b.eq(other)
         return pa.output
+
+    def __gt__(self, other):
+        print ("gt", self, other)
+        shape = self.sig.shape()
+        pa = PartitionedEqGtGe(shape[0], self.partpoints)
+        setattr(self.m.submodules, self.get_modname('gt'), pa)
+        comb = self.m.d.comb
+        comb += pa.opcode.eq(PartitionedEqGtGe.GT) # set opcode to GT
+        comb += pa.a.eq(self.sig)
+        if isinstance(other, PartitionedSignal):
+            comb += pa.b.eq(other.sig)
+        else:
+            comb += pa.b.eq(other)
+        return pa.output

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 4b46e1cee9b75f9d5fbfc715b8801b1a33abf4b7..1ec0cab40ec6b47ffca21f23645a8e1fd091e74d 100644 (file)
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -29,11 +29,13 @@ class TestAddMod(Elaboratable):
         self.b = PartitionedSignal(partpoints, width)
         self.add_output = Signal(width)
         self.eq_output = Signal(len(partpoints)+1)
+        self.gt_output = Signal(len(partpoints)+1)
 
     def elaborate(self, platform):
         m = Module()
         self.a.set_module(m)
         self.b.set_module(m)
+        m.d.comb += self.gt_output.eq(self.a > self.b)
         m.d.comb += self.eq_output.eq(self.a == self.b)
         m.d.comb += self.add_output.eq(self.a + self.b)
 
@@ -117,6 +119,44 @@ class TestPartitionPoints(unittest.TestCase):
             yield part_mask.eq(0b1111)
             yield from test_eq("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
 
+            def test_gt(msg_prefix, *maskbit_list):
+                for a, b in [(0x0000, 0x0000),
+                             (0x1234, 0x1234),
+                             (0xABCD, 0xABCD),
+                             (0xFFFF, 0x0000),
+                             (0x0000, 0x0000),
+                             (0xFFFF, 0xFFFF),
+                             (0x0000, 0xFFFF)]:
+                    yield module.a.eq(a)
+                    yield module.b.eq(b)
+                    yield Delay(0.1e-6)
+                    # convert to mask_list
+                    mask_list = []
+                    for mb in maskbit_list:
+                        v = 0
+                        for i in range(4):
+                            if mb & (1<<i):
+                                v |= 0xf << (i*4)
+                        mask_list.append(v)
+                    y = 0
+                    # do the partitioned tests
+                    for i, mask in enumerate(mask_list):
+                        if (a & mask) > (b & mask):
+                            # OR y with the lowest set bit in the mask
+                            y |= (maskbit_list[i] & ~(maskbit_list[i]-1))
+                    # check the result
+                    outval = (yield module.eq_output)
+                    msg = f"{msg_prefix}: 0x{a:X} == 0x{b:X}" + \
+                        f" => 0x{y:X} != 0x{outval:X}, masklist %s"
+                    #print ((msg % str(maskbit_list)).format(locals()))
+                    self.assertEqual(y, outval, msg % str(maskbit_list))
+            yield part_mask.eq(0)
+            yield from test_eq("16-bit", 0b1111)
+            yield part_mask.eq(0b10)
+            yield from test_eq("8-bit", 0b1100, 0b0011)
+            yield part_mask.eq(0b1111)
+            yield from test_eq("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
+
         sim.add_process(async_process)
         sim.run()