architecture behaviour of execute1 is
type reg_type is record
e : Execute1ToWritebackType;
- f : Execute1ToFetch1Type;
+ cur_instr : Decode2ToExecute1Type;
busy: std_ulogic;
terminate: std_ulogic;
fp_exception_next : std_ulogic;
mul_finish : std_ulogic;
div_in_progress : std_ulogic;
cntz_in_progress : std_ulogic;
- slow_op_insn : insn_type_t;
- slow_op_dest : gpr_index_t;
- slow_op_rc : std_ulogic;
- slow_op_oe : std_ulogic;
- slow_op_xerc : xer_common_t;
last_nia : std_ulogic_vector(63 downto 0);
+ redirect : std_ulogic;
+ abs_br : std_ulogic;
+ taken_br : std_ulogic;
+ br_last : std_ulogic;
+ do_intr : std_ulogic;
+ vector : integer range 0 to 16#fff#;
+ br_offset : std_ulogic_vector(63 downto 0);
+ redir_mode : std_ulogic_vector(3 downto 0);
log_addr_spr : std_ulogic_vector(31 downto 0);
end record;
constant reg_type_init : reg_type :=
- (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
+ (e => Execute1ToWritebackInit,
+ cur_instr => Decode2ToExecute1Init,
busy => '0', lr_update => '0', terminate => '0',
fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
- slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
- next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
+ next_lr => (others => '0'), last_nia => (others => '0'),
+ redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
+ br_offset => (others => '0'), redir_mode => "0000",
+ others => (others => '0'));
signal r, rin : reg_type;
signal rotator_carry: std_ulogic;
signal logical_result: std_ulogic_vector(63 downto 0);
signal countzero_result: std_ulogic_vector(63 downto 0);
+ signal alu_result: std_ulogic_vector(63 downto 0);
+ signal adder_result: std_ulogic_vector(63 downto 0);
+ signal misc_result: std_ulogic_vector(63 downto 0);
+ signal muldiv_result: std_ulogic_vector(63 downto 0);
+ signal spr_result: std_ulogic_vector(63 downto 0);
+ signal result_mux_sel: std_ulogic_vector(2 downto 0);
+ signal sub_mux_sel: std_ulogic_vector(2 downto 0);
+ signal current: Decode2ToExecute1Type;
-- multiply signals
signal x_to_multiply: MultiplyInputType;
terminate_out <= r.terminate;
+ current <= e_in when r.busy = '0' else r.cur_instr;
+
+ -- Result mux
+ with current.result_sel select alu_result <=
+ adder_result when "000",
+ logical_result when "001",
+ rotator_result when "010",
+ muldiv_result when "011",
+ countzero_result when "100",
+ spr_result when "101",
+ misc_result when others;
+
execute1_0: process(clk)
begin
if rising_edge(clk) then
execute1_1: process(all)
variable v : reg_type;
variable a_inv : std_ulogic_vector(63 downto 0);
- variable result : std_ulogic_vector(63 downto 0);
+ variable b_or_m1 : std_ulogic_vector(63 downto 0);
+ variable addg6s : std_ulogic_vector(63 downto 0);
+ variable isel_result : std_ulogic_vector(63 downto 0);
+ variable darn : std_ulogic_vector(63 downto 0);
+ variable mfcr_result : std_ulogic_vector(63 downto 0);
+ variable setb_result : std_ulogic_vector(63 downto 0);
variable newcrf : std_ulogic_vector(3 downto 0);
variable sum_with_carry : std_ulogic_vector(64 downto 0);
- variable result_en : std_ulogic;
variable crnum : crnum_t;
variable crbit : integer range 0 to 31;
variable scrnum : crnum_t;
variable zerohi, zerolo : std_ulogic;
variable msb_a, msb_b : std_ulogic;
variable a_lt : std_ulogic;
+ variable a_lt_lo : std_ulogic;
+ variable a_lt_hi : std_ulogic;
variable lv : Execute1ToLoadstore1Type;
variable irq_valid : std_ulogic;
variable exception : std_ulogic;
variable trapval : std_ulogic_vector(4 downto 0);
variable illegal : std_ulogic;
variable is_branch : std_ulogic;
+ variable is_direct_branch : std_ulogic;
variable taken_branch : std_ulogic;
variable abs_branch : std_ulogic;
variable spr_val : std_ulogic_vector(63 downto 0);
variable addend : std_ulogic_vector(127 downto 0);
variable do_trace : std_ulogic;
+ variable hold_wr_data : std_ulogic;
+ variable f : Execute1ToFetch1Type;
variable fv : Execute1ToFPUType;
begin
- result := (others => '0');
sum_with_carry := (others => '0');
- result_en := '0';
newcrf := (others => '0');
is_branch := '0';
+ is_direct_branch := '0';
taken_branch := '0';
abs_branch := '0';
+ hold_wr_data := '0';
v := r;
v.e := Execute1ToWritebackInit;
+ v.redirect := '0';
+ v.abs_br := '0';
+ v.do_intr := '0';
+ v.vector := 0;
+ v.br_offset := (others => '0');
+ v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
+ not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
+ v.taken_br := '0';
+ v.br_last := '0';
+
lv := Execute1ToLoadstore1Init;
- v.f.redirect := '0';
fv := Execute1ToFPUInit;
-- XER forwarding. To avoid having to track XER hazards, we use
-- (SO, OV[32] and CA[32]) are only modified by instructions that are
-- handled here, we can just forward the result being sent to
-- writeback.
- if r.e.write_xerc_enable = '1' then
+ if r.e.write_xerc_enable = '1' or r.busy = '1' then
v.e.xerc := r.e.xerc;
else
v.e.xerc := e_in.xerc;
v.cntz_in_progress := '0';
v.mul_finish := '0';
+ spr_result <= (others => '0');
+ spr_val := (others => '0');
+
-- Main adder
if e_in.invert_a = '0' then
a_inv := a_in;
else
a_inv := not a_in;
end if;
- sum_with_carry := ppc_adde(a_inv, b_in,
+ if e_in.addm1 = '0' then
+ b_or_m1 := b_in;
+ else
+ b_or_m1 := (others => '1');
+ end if;
+ sum_with_carry := ppc_adde(a_inv, b_or_m1,
decode_input_carry(e_in.input_carry, v.e.xerc));
+ adder_result <= sum_with_carry(63 downto 0);
+ carry_32 := sum_with_carry(32) xor a_inv(32) xor b_in(32);
+ carry_64 := sum_with_carry(64);
-- signals to multiply and divide units
sign1 := '0';
abs2 := - signed(b_in);
end if;
+ -- Interface to multiply and divide units
x_to_multiply <= MultiplyInputInit;
x_to_multiply.is_32bit <= e_in.is_32bit;
x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
end if;
+ case current.sub_select(1 downto 0) is
+ when "00" =>
+ muldiv_result <= multiply_to_x.result(63 downto 0);
+ when "01" =>
+ muldiv_result <= multiply_to_x.result(127 downto 64);
+ when "10" =>
+ muldiv_result <= multiply_to_x.result(63 downto 32) &
+ multiply_to_x.result(63 downto 32);
+ when others =>
+ muldiv_result <= divider_to_x.write_reg_data;
+ end case;
+
+ -- Compute misc_result
+ case current.sub_select is
+ when "000" =>
+ misc_result <= (others => '0');
+ when "001" =>
+ -- addg6s
+ addg6s := (others => '0');
+ for i in 0 to 14 loop
+ lo := i * 4;
+ hi := (i + 1) * 4;
+ if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
+ addg6s(lo + 3 downto lo) := "0110";
+ end if;
+ end loop;
+ if sum_with_carry(64) = '0' then
+ addg6s(63 downto 60) := "0110";
+ end if;
+ misc_result <= addg6s;
+ when "010" =>
+ -- isel
+ crbit := to_integer(unsigned(insn_bc(e_in.insn)));
+ if cr_in(31-crbit) = '1' then
+ isel_result := a_in;
+ else
+ isel_result := b_in;
+ end if;
+ misc_result <= isel_result;
+ when "011" =>
+ -- darn
+ darn := (others => '1');
+ if random_err = '0' then
+ case e_in.insn(17 downto 16) is
+ when "00" =>
+ darn := x"00000000" & random_cond(31 downto 0);
+ when "10" =>
+ darn := random_raw;
+ when others =>
+ darn := random_cond;
+ end case;
+ end if;
+ misc_result <= darn;
+ when "100" =>
+ -- mfmsr
+ misc_result <= ctrl.msr;
+ when "101" =>
+ if e_in.insn(20) = '0' then
+ -- mfcr
+ mfcr_result := x"00000000" & cr_in;
+ else
+ -- mfocrf
+ crnum := fxm_to_num(insn_fxm(e_in.insn));
+ mfcr_result := (others => '0');
+ for i in 0 to 7 loop
+ lo := (7-i)*4;
+ hi := lo + 3;
+ if crnum = i then
+ mfcr_result(hi downto lo) := cr_in(hi downto lo);
+ end if;
+ end loop;
+ end if;
+ misc_result <= mfcr_result;
+ when "110" =>
+ -- setb
+ bfa := insn_bfa(e_in.insn);
+ crbit := to_integer(unsigned(bfa)) * 4;
+ setb_result := (others => '0');
+ if cr_in(31 - crbit) = '1' then
+ setb_result := (others => '1');
+ elsif cr_in(30 - crbit) = '1' then
+ setb_result(0) := '1';
+ end if;
+ misc_result <= setb_result;
+ when others =>
+ misc_result <= (others => '0');
+ end case;
+
+ -- compute comparison results
+ -- Note, we have done RB - RA, not RA - RB
+ if e_in.insn_type = OP_CMP then
+ l := insn_l(e_in.insn);
+ else
+ l := not e_in.is_32bit;
+ end if;
+ zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
+ zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
+ if zerolo = '1' and (l = '0' or zerohi = '1') then
+ -- values are equal
+ trapval := "00100";
+ else
+ a_lt_lo := '0';
+ a_lt_hi := '0';
+ if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
+ a_lt_lo := '1';
+ end if;
+ if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
+ a_lt_hi := '1';
+ end if;
+ if l = '1' then
+ -- 64-bit comparison
+ msb_a := a_in(63);
+ msb_b := b_in(63);
+ a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
+ else
+ -- 32-bit comparison
+ msb_a := a_in(31);
+ msb_b := b_in(31);
+ a_lt := a_lt_lo;
+ end if;
+ if msb_a /= msb_b then
+ -- Comparison is clear from MSB difference.
+ -- for signed, 0 is greater; for unsigned, 1 is greater
+ trapval := msb_a & msb_b & '0' & msb_b & msb_a;
+ else
+ -- MSBs are equal, so signed and unsigned comparisons give the
+ -- same answer.
+ trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
+ end if;
+ end if;
+
ctrl_tmp <= ctrl;
-- FIXME: run at 512MHz not core freq
ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
irq_valid := '0';
if ctrl.msr(MSR_EE) = '1' then
if ctrl.dec(63) = '1' then
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
+ v.vector := 16#900#;
report "IRQ valid: DEC";
irq_valid := '1';
elsif ext_irq_in = '1' then
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
+ v.vector := 16#500#;
report "IRQ valid: External";
irq_valid := '1';
end if;
v.terminate := '0';
icache_inval <= '0';
v.busy := '0';
- -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
- v.f.virt_mode := ctrl.msr(MSR_IR);
- v.f.priv_mode := not ctrl.msr(MSR_PR);
- v.f.big_endian := not ctrl.msr(MSR_LE);
- v.f.mode_32bit := not ctrl.msr(MSR_SF);
-- Next insn adder used in a couple of places
next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
v.prev_op := e_in.insn_type;
end if;
- if ctrl.irq_state = WRITE_SRR1 then
- v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
- v.e.exc_write_data := ctrl.srr1;
- v.e.exc_write_enable := '1';
- ctrl_tmp.msr(MSR_SF) <= '1';
- ctrl_tmp.msr(MSR_EE) <= '0';
- ctrl_tmp.msr(MSR_PR) <= '0';
- ctrl_tmp.msr(MSR_SE) <= '0';
- ctrl_tmp.msr(MSR_BE) <= '0';
- ctrl_tmp.msr(MSR_FP) <= '0';
- ctrl_tmp.msr(MSR_FE0) <= '0';
- ctrl_tmp.msr(MSR_FE1) <= '0';
- ctrl_tmp.msr(MSR_IR) <= '0';
- ctrl_tmp.msr(MSR_DR) <= '0';
- ctrl_tmp.msr(MSR_RI) <= '0';
- ctrl_tmp.msr(MSR_LE) <= '1';
- v.e.valid := '1';
- v.trace_next := '0';
- v.fp_exception_next := '0';
- report "Writing SRR1: " & to_hstring(ctrl.srr1);
-
- elsif valid_in = '1' and e_in.second = '0' and
- ((HAS_FPU and r.fp_exception_next = '1') or r.trace_next = '1') then
+ -- Determine if there is any exception to be taken
+ -- before/instead of executing this instruction
+ if valid_in = '1' and e_in.second = '0' then
if HAS_FPU and r.fp_exception_next = '1' then
-- This is used for FP-type program interrupts that
-- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
+ exception := '1';
+ v.vector := 16#700#;
ctrl_tmp.srr1(63 - 43) <= '1';
ctrl_tmp.srr1(63 - 47) <= '1';
- else
+ elsif r.trace_next = '1' then
-- Generate a trace interrupt rather than executing the next instruction
-- or taking any asynchronous interrupt
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
+ exception := '1';
+ v.vector := 16#d00#;
ctrl_tmp.srr1(63 - 33) <= '1';
if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
ctrl_tmp.srr1(63 - 36) <= '1';
end if;
- end if;
- exception := '1';
- elsif irq_valid = '1' and valid_in = '1' and e_in.second = '0' then
- -- we need two cycles to write srr0 and 1
- -- will need more when we have to write HEIR
- -- Don't deliver the interrupt until we have a valid instruction
- -- coming in, so we have a valid NIA to put in SRR0.
- exception := '1';
-
- elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
- instr_is_privileged(e_in.insn_type, e_in.insn) then
- -- generate a program interrupt
- exception := '1';
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
- -- set bit 45 to indicate privileged instruction type interrupt
- ctrl_tmp.srr1(63 - 45) <= '1';
- report "privileged instruction";
-
- elsif not HAS_FPU and valid_in = '1' and e_in.fac = FPU then
- -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
- illegal := '1';
-
- elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
- -- generate a floating-point unavailable interrupt
- exception := '1';
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#800#, 64));
- report "FP unavailable interrupt";
+ elsif irq_valid = '1' then
+ -- Don't deliver the interrupt until we have a valid instruction
+ -- coming in, so we have a valid NIA to put in SRR0.
+ exception := '1';
+
+ elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
+ -- generate a program interrupt
+ exception := '1';
+ v.vector := 16#700#;
+ -- set bit 45 to indicate privileged instruction type interrupt
+ ctrl_tmp.srr1(63 - 45) <= '1';
+ report "privileged instruction";
+
+ elsif not HAS_FPU and e_in.fac = FPU then
+ -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
+ illegal := '1';
- elsif valid_in = '1' and e_in.unit = ALU then
+ elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
+ -- generate a floating-point unavailable interrupt
+ exception := '1';
+ v.vector := 16#800#;
+ report "FP unavailable interrupt";
+ end if;
+ end if;
+ if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
report "execute nia " & to_hstring(e_in.nia);
+ v.cur_instr := e_in;
+ v.next_lr := next_nia;
v.e.valid := '1';
- v.e.write_reg := e_in.write_reg;
- v.slow_op_insn := e_in.insn_type;
- v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
- v.slow_op_rc := e_in.rc;
- v.slow_op_oe := e_in.oe;
- v.slow_op_xerc := v.e.xerc;
case_0: case e_in.insn_type is
if e_in.insn(1) = '1' then
exception := '1';
exception_nextpc := '1';
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
+ v.vector := 16#C00#;
report "sc";
else
illegal := '1';
end if;
when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
-- Do nothing
- when OP_ADD | OP_CMP | OP_TRAP =>
- result := sum_with_carry(63 downto 0);
- carry_32 := result(32) xor a_inv(32) xor b_in(32);
- carry_64 := sum_with_carry(64);
- if e_in.insn_type = OP_ADD then
- if e_in.output_carry = '1' then
- if e_in.input_carry /= OV then
- set_carry(v.e, carry_32, carry_64);
- else
- v.e.xerc.ov := carry_64;
- v.e.xerc.ov32 := carry_32;
- v.e.write_xerc_enable := '1';
- end if;
- end if;
- if e_in.oe = '1' then
- set_ov(v.e,
- calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
- calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
- end if;
- result_en := '1';
- else
- -- trap, CMP and CMPL instructions
- -- Note, we have done RB - RA, not RA - RB
- if e_in.insn_type = OP_CMP then
- l := insn_l(e_in.insn);
- else
- l := not e_in.is_32bit;
- end if;
- zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
- zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
- if zerolo = '1' and (l = '0' or zerohi = '1') then
- -- values are equal
- trapval := "00100";
+ when OP_ADD =>
+ if e_in.output_carry = '1' then
+ if e_in.input_carry /= OV then
+ set_carry(v.e, carry_32, carry_64);
else
- if l = '1' then
- -- 64-bit comparison
- msb_a := a_in(63);
- msb_b := b_in(63);
- else
- -- 32-bit comparison
- msb_a := a_in(31);
- msb_b := b_in(31);
- end if;
- if msb_a /= msb_b then
- -- Subtraction might overflow, but
- -- comparison is clear from MSB difference.
- -- for signed, 0 is greater; for unsigned, 1 is greater
- trapval := msb_a & msb_b & '0' & msb_b & msb_a;
- else
- -- Subtraction cannot overflow since MSBs are equal.
- -- carry = 1 indicates RA is smaller (signed or unsigned)
- a_lt := (not l and carry_32) or (l and carry_64);
- trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
- end if;
- end if;
- if e_in.insn_type = OP_CMP then
- if e_in.is_signed = '1' then
- newcrf := trapval(4 downto 2) & v.e.xerc.so;
- else
- newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
- end if;
- bf := insn_bf(e_in.insn);
- crnum := to_integer(unsigned(bf));
- v.e.write_cr_enable := '1';
- v.e.write_cr_mask := num_to_fxm(crnum);
- for i in 0 to 7 loop
- lo := i*4;
- hi := lo + 3;
- v.e.write_cr_data(hi downto lo) := newcrf;
- end loop;
- else
- -- trap instructions (tw, twi, td, tdi)
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
- -- set bit 46 to say trap occurred
- ctrl_tmp.srr1(63 - 46) <= '1';
- if or (trapval and insn_to(e_in.insn)) = '1' then
- -- generate trap-type program interrupt
- exception := '1';
- report "trap";
- end if;
+ v.e.xerc.ov := carry_64;
+ v.e.xerc.ov32 := carry_32;
+ v.e.write_xerc_enable := '1';
end if;
end if;
- when OP_ADDG6S =>
- result := (others => '0');
- for i in 0 to 14 loop
- lo := i * 4;
- hi := (i + 1) * 4;
- if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
- result(lo + 3 downto lo) := "0110";
- end if;
+ if e_in.oe = '1' then
+ set_ov(v.e,
+ calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
+ calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
+ end if;
+ when OP_CMP =>
+ -- CMP and CMPL instructions
+ if e_in.is_signed = '1' then
+ newcrf := trapval(4 downto 2) & v.e.xerc.so;
+ else
+ newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
+ end if;
+ bf := insn_bf(e_in.insn);
+ crnum := to_integer(unsigned(bf));
+ v.e.write_cr_enable := '1';
+ v.e.write_cr_mask := num_to_fxm(crnum);
+ for i in 0 to 7 loop
+ lo := i*4;
+ hi := lo + 3;
+ v.e.write_cr_data(hi downto lo) := newcrf;
end loop;
- if sum_with_carry(64) = '0' then
- result(63 downto 60) := "0110";
+ when OP_TRAP =>
+ -- trap instructions (tw, twi, td, tdi)
+ v.vector := 16#700#;
+ -- set bit 46 to say trap occurred
+ ctrl_tmp.srr1(63 - 46) <= '1';
+ if or (trapval and insn_to(e_in.insn)) = '1' then
+ -- generate trap-type program interrupt
+ exception := '1';
+ report "trap";
end if;
- result_en := '1';
+ when OP_ADDG6S =>
when OP_CMPRB =>
newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
bf := insn_bf(e_in.insn);
newcrf & newcrf & newcrf & newcrf;
when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
OP_BPERM | OP_BCD =>
- result := logical_result;
- result_en := '1';
when OP_B =>
is_branch := '1';
taken_branch := '1';
+ is_direct_branch := '1';
abs_branch := insn_aa(e_in.insn);
if ctrl.msr(MSR_BE) = '1' then
do_trace := '1';
-- read_data1 is CTR
bo := insn_bo(e_in.insn);
bi := insn_bi(e_in.insn);
- if bo(4-2) = '0' then
- result := std_ulogic_vector(unsigned(a_in) - 1);
- result_en := '1';
- v.e.write_reg := fast_spr_num(SPR_CTR);
- end if;
is_branch := '1';
+ is_direct_branch := '1';
taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
abs_branch := insn_aa(e_in.insn);
if ctrl.msr(MSR_BE) = '1' then
-- read_data2 is target register (CTR, LR or TAR)
bo := insn_bo(e_in.insn);
bi := insn_bi(e_in.insn);
- if bo(4-2) = '0' and e_in.insn(10) = '0' then
- result := std_ulogic_vector(unsigned(a_in) - 1);
- result_en := '1';
- v.e.write_reg := fast_spr_num(SPR_CTR);
- end if;
is_branch := '1';
taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
abs_branch := '1';
end if;
when OP_RFID =>
- v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
- v.f.priv_mode := not a_in(MSR_PR);
- v.f.big_endian := not a_in(MSR_LE);
- v.f.mode_32bit := not a_in(MSR_SF);
+ v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
+ not a_in(MSR_LE) & not a_in(MSR_SF);
-- Can't use msr_copy here because the partial function MSR
-- bits should be left unchanged, not zeroed.
ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
v.cntz_in_progress := '1';
v.busy := '1';
when OP_ISEL =>
- crbit := to_integer(unsigned(insn_bc(e_in.insn)));
- if cr_in(31-crbit) = '1' then
- result := a_in;
- else
- result := b_in;
- end if;
- result_en := '1';
when OP_CROP =>
cr_op := insn_cr(e_in.insn);
report "CR OP " & to_hstring(cr_op);
v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
newcrf & newcrf & newcrf & newcrf;
when OP_DARN =>
- if random_err = '0' then
- case e_in.insn(17 downto 16) is
- when "00" =>
- result := x"00000000" & random_cond(31 downto 0);
- when "10" =>
- result := random_raw;
- when others =>
- result := random_cond;
- end case;
- else
- result := (others => '1');
- end if;
- result_en := '1';
when OP_MFMSR =>
- result := ctrl.msr;
- result_en := '1';
when OP_MFSPR =>
report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
"=" & to_hstring(a_in);
- result_en := '1';
- if is_fast_spr(e_in.read_reg1) then
- result := a_in;
- if decode_spr_num(e_in.insn) = SPR_XER then
+ if is_fast_spr(e_in.read_reg1) = '1' then
+ spr_val := a_in;
+ if decode_spr_num(e_in.insn) = SPR_XER then
-- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
- result(63 downto 32) := (others => '0');
- result(63-32) := v.e.xerc.so;
- result(63-33) := v.e.xerc.ov;
- result(63-34) := v.e.xerc.ca;
- result(63-35 downto 63-43) := "000000000";
- result(63-44) := v.e.xerc.ov32;
- result(63-45) := v.e.xerc.ca32;
- end if;
+ spr_val(63 downto 32) := (others => '0');
+ spr_val(63-32) := v.e.xerc.so;
+ spr_val(63-33) := v.e.xerc.ov;
+ spr_val(63-34) := v.e.xerc.ca;
+ spr_val(63-35 downto 63-43) := "000000000";
+ spr_val(63-44) := v.e.xerc.ov32;
+ spr_val(63-45) := v.e.xerc.ca32;
+ end if;
else
spr_val := c_in;
- case decode_spr_num(e_in.insn) is
+ case decode_spr_num(e_in.insn) is
when SPR_TB =>
spr_val := ctrl.tb;
when SPR_TBU =>
when others =>
-- mfspr from unimplemented SPRs should be a nop in
-- supervisor mode and a program interrupt for user mode
- if ctrl.msr(MSR_PR) = '1' then
+ if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
illegal := '1';
end if;
- end case;
- result := spr_val;
- end if;
+ end case;
+ end if;
+ spr_result <= spr_val;
+
when OP_MFCR =>
- if e_in.insn(20) = '0' then
- -- mfcr
- result := x"00000000" & cr_in;
- else
- -- mfocrf
- crnum := fxm_to_num(insn_fxm(e_in.insn));
- result := (others => '0');
- for i in 0 to 7 loop
- lo := (7-i)*4;
- hi := lo + 3;
- if crnum = i then
- result(hi downto lo) := cr_in(hi downto lo);
- end if;
- end loop;
- end if;
- result_en := '1';
when OP_MTCRF =>
v.e.write_cr_enable := '1';
if e_in.insn(20) = '0' then
report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
"=" & to_hstring(c_in);
if is_fast_spr(e_in.write_reg) then
- result := c_in;
- result_en := '1';
if decode_spr_num(e_in.insn) = SPR_XER then
v.e.xerc.so := c_in(63-32);
v.e.xerc.ov := c_in(63-33);
end case;
end if;
when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
- result := rotator_result;
if e_in.output_carry = '1' then
set_carry(v.e, rotator_carry, rotator_carry);
end if;
- result_en := '1';
when OP_SETB =>
- bfa := insn_bfa(e_in.insn);
- crbit := to_integer(unsigned(bfa)) * 4;
- result := (others => '0');
- if cr_in(31 - crbit) = '1' then
- result := (others => '1');
- elsif cr_in(30 - crbit) = '1' then
- result(0) := '1';
- end if;
when OP_ISYNC =>
- v.f.redirect := '1';
- v.f.redirect_nia := next_nia;
+ v.redirect := '1';
+ v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
when OP_ICBI =>
icache_inval <= '1';
report "illegal";
end case;
- v.e.rc := e_in.rc and valid_in;
-
-- Mispredicted branches cause a redirect
if is_branch = '1' then
if taken_branch = '1' then
ctrl_tmp.cfar <= e_in.nia;
end if;
- if e_in.br_pred = '0' then
- if abs_branch = '1' then
- v.f.redirect_nia := b_in;
- else
- v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
- end if;
+ if taken_branch = '1' then
+ v.br_offset := b_in;
+ v.abs_br := abs_branch;
else
- v.f.redirect_nia := next_nia;
+ v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
end if;
if taken_branch /= e_in.br_pred then
- v.f.redirect := '1';
+ v.redirect := '1';
end if;
+ v.br_last := is_direct_branch;
+ v.taken_br := taken_branch;
end if;
- -- Update LR on the next cycle after a branch link
- -- If we're not writing back anything else, we can write back LR
- -- this cycle, otherwise we take an extra cycle. We use the
- -- exc_write path since next_nia is written through that path
- -- in other places.
- if e_in.lr = '1' then
- if result_en = '0' then
- v.e.exc_write_enable := '1';
- v.e.exc_write_data := next_nia;
- v.e.exc_write_reg := fast_spr_num(SPR_LR);
- else
- v.lr_update := '1';
- v.next_lr := next_nia;
- v.e.valid := '0';
- report "Delayed LR update to " & to_hstring(next_nia);
- v.busy := '1';
- end if;
- end if;
-
- elsif valid_in = '1' then
+ elsif valid_in = '1' and exception = '0' and illegal = '0' then
-- instruction for other units, i.e. LDST
if e_in.unit = LDST then
lv.valid := '1';
-- valid_in = 0. Hence they don't happen in the same cycle as any of
-- the cases above which depend on valid_in = 1.
- if r.f.redirect = '1' then
- v.e.valid := '1';
- end if;
- if r.lr_update = '1' then
+ if ctrl.irq_state = WRITE_SRR1 then
+ v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
+ v.e.exc_write_data := ctrl.srr1;
v.e.exc_write_enable := '1';
- v.e.exc_write_data := r.next_lr;
- v.e.exc_write_reg := fast_spr_num(SPR_LR);
- v.e.valid := '1';
- -- Keep r.e.write_data unchanged next cycle in case it is needed
- -- for a forwarded result (e.g. for CTR).
- result := r.e.write_data;
+ ctrl_tmp.msr(MSR_SF) <= '1';
+ ctrl_tmp.msr(MSR_EE) <= '0';
+ ctrl_tmp.msr(MSR_PR) <= '0';
+ ctrl_tmp.msr(MSR_SE) <= '0';
+ ctrl_tmp.msr(MSR_BE) <= '0';
+ ctrl_tmp.msr(MSR_FP) <= '0';
+ ctrl_tmp.msr(MSR_FE0) <= '0';
+ ctrl_tmp.msr(MSR_FE1) <= '0';
+ ctrl_tmp.msr(MSR_IR) <= '0';
+ ctrl_tmp.msr(MSR_DR) <= '0';
+ ctrl_tmp.msr(MSR_RI) <= '0';
+ ctrl_tmp.msr(MSR_LE) <= '1';
+ v.trace_next := '0';
+ v.fp_exception_next := '0';
+ report "Writing SRR1: " & to_hstring(ctrl.srr1);
+
elsif r.cntz_in_progress = '1' then
-- cnt[lt]z always takes two cycles
- result := countzero_result;
- result_en := '1';
- v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
- v.e.rc := r.slow_op_rc;
- v.e.xerc := r.slow_op_xerc;
v.e.valid := '1';
elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
(r.div_in_progress = '1' and divider_to_x.valid = '1') then
if r.mul_in_progress = '1' then
overflow := '0';
- case r.slow_op_insn is
- when OP_MUL_H32 =>
- result := multiply_to_x.result(63 downto 32) &
- multiply_to_x.result(63 downto 32);
- when OP_MUL_H64 =>
- result := multiply_to_x.result(127 downto 64);
- when others =>
- -- i.e. OP_MUL_L64
- result := multiply_to_x.result(63 downto 0);
- end case;
else
- result := divider_to_x.write_reg_data;
overflow := divider_to_x.overflow;
end if;
- if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
+ if r.mul_in_progress = '1' and current.oe = '1' then
-- have to wait until next cycle for overflow indication
v.mul_finish := '1';
v.busy := '1';
else
- result_en := '1';
- v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
- v.e.rc := r.slow_op_rc;
- v.e.xerc := r.slow_op_xerc;
- v.e.write_xerc_enable := r.slow_op_oe;
+ v.e.write_xerc_enable := current.oe;
-- We must test oe because the RC update code in writeback
-- will use the xerc value to set CR0:SO so we must not clobber
-- xerc if OE wasn't set.
- if r.slow_op_oe = '1' then
+ if current.oe = '1' then
v.e.xerc.ov := overflow;
v.e.xerc.ov32 := overflow;
- v.e.xerc.so := r.slow_op_xerc.so or overflow;
+ if overflow = '1' then
+ v.e.xerc.so := '1';
+ end if;
end if;
v.e.valid := '1';
end if;
v.div_in_progress := r.div_in_progress;
end if;
elsif r.mul_finish = '1' then
- result := r.e.write_data;
- result_en := '1';
- v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
- v.e.rc := r.slow_op_rc;
- v.e.xerc := r.slow_op_xerc;
- v.e.write_xerc_enable := r.slow_op_oe;
+ hold_wr_data := '1';
+ v.e.write_xerc_enable := current.oe;
v.e.xerc.ov := multiply_to_x.overflow;
v.e.xerc.ov32 := multiply_to_x.overflow;
- v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
+ if multiply_to_x.overflow = '1' then
+ v.e.xerc.so := '1';
+ end if;
v.e.valid := '1';
end if;
+ -- When doing delayed LR update, keep r.e.write_data unchanged
+ -- next cycle in case it is needed for a forwarded result (e.g. CTR).
+ if r.lr_update = '1' then
+ hold_wr_data := '1';
+ end if;
-- Generate FP-type program interrupt. fp_in.interrupt will only
-- be set during the execution of a FP instruction.
-- The case where MSR[FE0,FE1] goes from zero to non-zero is
-- handled above by mtmsrd and rfid setting v.fp_exception_next.
if HAS_FPU and fp_in.interrupt = '1' then
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
+ v.vector := 16#700#;
ctrl_tmp.srr1(63 - 43) <= '1';
exception := '1';
end if;
if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
exception := '1';
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
+ v.vector := 16#700#;
-- Since we aren't doing Hypervisor emulation assist (0xe40) we
-- set bit 44 to indicate we have an illegal
ctrl_tmp.srr1(63 - 44) <= '1';
end if;
end if;
- if do_trace = '1' then
- v.trace_next := '1';
- end if;
-
- v.e.write_data := result;
- v.e.write_enable := result_en and not exception;
-
-- generate DSI or DSegI for load/store exceptions
-- or ISI or ISegI for instruction fetch exceptions
if l_in.exception = '1' then
if l_in.alignment = '1' then
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
+ v.vector := 16#600#;
elsif l_in.instr_fault = '0' then
if l_in.segment_fault = '0' then
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
+ v.vector := 16#300#;
else
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
+ v.vector := 16#380#;
end if;
else
if l_in.segment_fault = '0' then
ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
+ v.vector := 16#400#;
else
- v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
+ v.vector := 16#480#;
end if;
end if;
v.e.exc_write_enable := '1';
if exception = '1' or l_in.exception = '1' then
ctrl_tmp.irq_state <= WRITE_SRR1;
- v.f.redirect := '1';
- v.f.virt_mode := '0';
- v.f.priv_mode := '1';
- -- XXX need an interrupt LE bit here, e.g. from LPCR
- v.f.big_endian := '0';
- v.f.mode_32bit := '0';
+ v.redirect := '1';
+ v.do_intr := '1';
+ end if;
+
+ if do_trace = '1' then
+ v.trace_next := '1';
+ end if;
+
+ if hold_wr_data = '0' then
+ v.e.write_data := alu_result;
+ else
+ v.e.write_data := r.e.write_data;
+ end if;
+ v.e.write_reg := current.write_reg;
+ v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
+ v.e.rc := current.rc and v.e.valid and not exception;
+
+ -- Update LR on the next cycle after a branch link
+ -- If we're not writing back anything else, we can write back LR
+ -- this cycle, otherwise we take an extra cycle. We use the
+ -- exc_write path since next_nia is written through that path
+ -- in other places.
+ if v.e.valid = '1' and exception = '0' and current.lr = '1' then
+ if current.write_reg_enable = '0' then
+ v.e.exc_write_enable := '1';
+ v.e.exc_write_data := next_nia;
+ v.e.exc_write_reg := fast_spr_num(SPR_LR);
+ else
+ v.lr_update := '1';
+ v.e.valid := '0';
+ report "Delayed LR update to " & to_hstring(next_nia);
+ v.busy := '1';
+ end if;
+ end if;
+ if r.lr_update = '1' then
+ v.e.exc_write_enable := '1';
+ v.e.exc_write_data := r.next_lr;
+ v.e.exc_write_reg := fast_spr_num(SPR_LR);
+ v.e.valid := '1';
end if;
- if v.f.redirect = '1' then
+ -- Defer completion for one cycle when redirecting.
+ -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
+ if v.redirect = '1' then
v.busy := '1';
v.e.valid := '0';
end if;
+ if r.redirect = '1' then
+ v.e.valid := '1';
+ end if;
+
+ -- Outputs to fetch1
+ f.redirect := r.redirect;
+ f.br_nia := r.last_nia;
+ f.br_last := r.br_last and not r.do_intr;
+ f.br_taken := r.taken_br;
+ if r.do_intr = '1' then
+ f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
+ f.virt_mode := '0';
+ f.priv_mode := '1';
+ -- XXX need an interrupt LE bit here, e.g. from LPCR
+ f.big_endian := '0';
+ f.mode_32bit := '0';
+ else
+ if r.abs_br = '1' then
+ f.redirect_nia := r.br_offset;
+ else
+ f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
+ end if;
+ -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
+ f.virt_mode := r.redir_mode(3);
+ f.priv_mode := r.redir_mode(2);
+ f.big_endian := r.redir_mode(1);
+ f.mode_32bit := r.redir_mode(0);
+ end if;
-- Outputs to loadstore1 (async)
lv.op := e_in.insn_type;
rin <= v;
-- update outputs
- f_out <= r.f;
+ f_out <= f;
l_out <= lv;
e_out <= r.e;
fp_out <= fv;
-- State machine for unaligned loads/stores
type state_t is (IDLE, -- ready for instruction
- FPR_CONV, -- converting double to float for store
SECOND_REQ, -- send 2nd request of unaligned xfer
ACK_WAIT, -- waiting for ack from dcache
MMU_LOOKUP, -- waiting for MMU to look up translation
COMPLETE -- extra cycle to complete an operation
);
+ type byte_index_t is array(0 to 7) of unsigned(2 downto 0);
+ subtype byte_trim_t is std_ulogic_vector(1 downto 0);
+ type trim_ctl_t is array(0 to 7) of byte_trim_t;
+
type reg_stage_t is record
-- latch most of the input request
load : std_ulogic;
tlbie : std_ulogic;
dcbz : std_ulogic;
- mfspr : std_ulogic;
addr : std_ulogic_vector(63 downto 0);
store_data : std_ulogic_vector(63 downto 0);
load_data : std_ulogic_vector(63 downto 0);
write_reg : gspr_index_t;
length : std_ulogic_vector(3 downto 0);
byte_reverse : std_ulogic;
+ byte_offset : unsigned(2 downto 0);
+ brev_mask : unsigned(2 downto 0);
sign_extend : std_ulogic;
update : std_ulogic;
update_reg : gpr_index_t;
do_update : std_ulogic;
extra_cycle : std_ulogic;
mode_32bit : std_ulogic;
+ byte_index : byte_index_t;
+ use_second : std_ulogic_vector(7 downto 0);
+ trim_ctl : trim_ctl_t;
load_sp : std_ulogic;
ld_sp_data : std_ulogic_vector(31 downto 0);
ld_sp_nz : std_ulogic;
ld_sp_lz : std_ulogic_vector(5 downto 0);
- st_sp_data : std_ulogic_vector(31 downto 0);
+ wr_sel : std_ulogic_vector(1 downto 0);
end record;
- type byte_sel_t is array(0 to 7) of std_ulogic;
- subtype byte_trim_t is std_ulogic_vector(1 downto 0);
- type trim_ctl_t is array(0 to 7) of byte_trim_t;
-
signal r, rin : reg_stage_t;
signal lsu_sum : std_ulogic_vector(63 downto 0);
variable data_permuted : std_ulogic_vector(63 downto 0);
variable data_trimmed : std_ulogic_vector(63 downto 0);
variable store_data : std_ulogic_vector(63 downto 0);
- variable data_in : std_ulogic_vector(63 downto 0);
variable byte_rev : std_ulogic;
variable length : std_ulogic_vector(3 downto 0);
- variable use_second : byte_sel_t;
- variable trim_ctl : trim_ctl_t;
variable negative : std_ulogic;
variable sprn : std_ulogic_vector(9 downto 0);
variable exception : std_ulogic;
variable mmu_mtspr : std_ulogic;
variable itlb_fault : std_ulogic;
variable misaligned : std_ulogic;
- variable fp_reg_conv : std_ulogic;
- variable lfs_done : std_ulogic;
begin
v := r;
req := '0';
- v.mfspr := '0';
mmu_mtspr := '0';
itlb_fault := '0';
sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
dsisr := (others => '0');
mmureq := '0';
- fp_reg_conv := '0';
+ v.wr_sel := "11";
write_enable := '0';
- lfs_done := '0';
do_update := r.do_update;
v.do_update := '0';
-- load data formatting
- byte_offset := unsigned(r.addr(2 downto 0));
- brev_lenm1 := "000";
- if r.byte_reverse = '1' then
- brev_lenm1 := unsigned(r.length(2 downto 0)) - 1;
- end if;
-
-- shift and byte-reverse data bytes
for i in 0 to 7 loop
- kk := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
- use_second(i) := kk(3);
- j := to_integer(kk(2 downto 0)) * 8;
+ j := to_integer(r.byte_index(i)) * 8;
data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
end loop;
-- trim and sign-extend
for i in 0 to 7 loop
- if i < to_integer(unsigned(r.length)) then
- if r.dwords_done = '1' then
- trim_ctl(i) := '1' & not use_second(i);
- else
- trim_ctl(i) := "10";
- end if;
- else
- trim_ctl(i) := '0' & (negative and r.sign_extend);
- end if;
- case trim_ctl(i) is
+ case r.trim_ctl(i) is
when "11" =>
data_trimmed(i * 8 + 7 downto i * 8) := r.load_data(i * 8 + 7 downto i * 8);
when "10" =>
data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
when "01" =>
- data_trimmed(i * 8 + 7 downto i * 8) := x"FF";
+ data_trimmed(i * 8 + 7 downto i * 8) := (others => negative);
when others =>
data_trimmed(i * 8 + 7 downto i * 8) := x"00";
end case;
end loop;
if HAS_FPU then
- -- Single-precision FP conversion
- v.st_sp_data := store_sp_data;
+ -- Single-precision FP conversion for loads
v.ld_sp_data := data_trimmed(31 downto 0);
v.ld_sp_nz := or (data_trimmed(22 downto 0));
v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
end if;
-- Byte reversing and rotating for stores.
- -- Done in the first cycle (when l_in.valid = 1) for integer stores
- -- and DP float stores, and in the second cycle for SP float stores.
- store_data := r.store_data;
- if l_in.valid = '1' or (HAS_FPU and r.state = FPR_CONV) then
- if HAS_FPU and r.state = FPR_CONV then
- data_in := x"00000000" & r.st_sp_data;
- byte_offset := unsigned(r.addr(2 downto 0));
- byte_rev := r.byte_reverse;
- length := r.length;
- else
- data_in := l_in.data;
- byte_offset := unsigned(lsu_sum(2 downto 0));
- byte_rev := l_in.byte_reverse;
- length := l_in.length;
- end if;
- brev_lenm1 := "000";
- if byte_rev = '1' then
- brev_lenm1 := unsigned(length(2 downto 0)) - 1;
- end if;
- for i in 0 to 7 loop
- k := (to_unsigned(i, 3) - byte_offset) xor brev_lenm1;
- j := to_integer(k) * 8;
- store_data(i * 8 + 7 downto i * 8) := data_in(j + 7 downto j);
- end loop;
- end if;
- v.store_data := store_data;
+ -- Done in the second cycle (the cycle after l_in.valid = 1).
+ for i in 0 to 7 loop
+ k := (to_unsigned(i, 3) - r.byte_offset) xor r.brev_mask;
+ j := to_integer(k) * 8;
+ store_data(i * 8 + 7 downto i * 8) := r.store_data(j + 7 downto j);
+ end loop;
-- compute (addr + 8) & ~7 for the second doubleword when unaligned
next_addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
case r.state is
when IDLE =>
- when FPR_CONV =>
- req := '1';
- if r.second_bytes /= "00000000" then
- v.state := SECOND_REQ;
- else
- v.state := ACK_WAIT;
- end if;
-
when SECOND_REQ =>
req := '1';
v.state := ACK_WAIT;
v.last_dword := '0';
when ACK_WAIT =>
+ -- r.wr_sel gets set one cycle after we come into ACK_WAIT state,
+ -- which is OK because the dcache always takes at least two cycles.
+ if r.update = '1' and (r.load = '0' or (HAS_FPU and r.load_sp = '1')) then
+ v.wr_sel := "01";
+ end if;
if d_in.error = '1' then
-- dcache will discard the second request if it
-- gets an error on the 1st of two requests
-- SP to DP conversion takes a cycle
-- Write back rA update in this cycle if needed
do_update := r.update;
+ v.wr_sel := "10";
v.state := FINISH_LFS;
elsif r.extra_cycle = '1' then
-- loads with rA update need an extra cycle
+ v.wr_sel := "01";
v.state := COMPLETE;
v.do_update := r.update;
else
when TLBIE_WAIT =>
when FINISH_LFS =>
- lfs_done := '1';
when COMPLETE =>
exception := r.align_intr;
v.do_update := '0';
v.extra_cycle := '0';
+ if HAS_FPU and l_in.is_32bit = '1' then
+ v.store_data := x"00000000" & store_sp_data;
+ else
+ v.store_data := l_in.data;
+ end if;
+
addr := lsu_sum;
if l_in.second = '1' then
-- for the second half of a 16-byte transfer, use next_addr
case l_in.op is
when OP_STORE =>
- if HAS_FPU and l_in.is_32bit = '1' then
- v.state := FPR_CONV;
- fp_reg_conv := '1';
- else
- req := '1';
- end if;
+ req := '1';
when OP_LOAD =>
req := '1';
v.load := '1';
v.state := TLBIE_WAIT;
v.wait_mmu := '1';
when OP_MFSPR =>
- v.mfspr := '1';
+ v.wr_sel := "00";
-- partial decode on SPR number should be adequate given
-- the restricted set that get sent down this path
if sprn(9) = '0' and sprn(5) = '0' then
end if;
end if;
- v.busy := req or mmureq or mmu_mtspr or fp_reg_conv;
+ v.busy := req or mmureq or mmu_mtspr;
+ end if;
+
+ -- Work out controls for store formatting
+ if l_in.valid = '1' then
+ byte_offset := unsigned(lsu_sum(2 downto 0));
+ byte_rev := l_in.byte_reverse;
+ length := l_in.length;
+ brev_lenm1 := "000";
+ if byte_rev = '1' then
+ brev_lenm1 := unsigned(length(2 downto 0)) - 1;
+ end if;
+ v.byte_offset := byte_offset;
+ v.brev_mask := brev_lenm1;
+ end if;
+
+ -- Work out load formatter controls for next cycle
+ byte_offset := unsigned(v.addr(2 downto 0));
+ brev_lenm1 := "000";
+ if v.byte_reverse = '1' then
+ brev_lenm1 := unsigned(v.length(2 downto 0)) - 1;
end if;
+ for i in 0 to 7 loop
+ kk := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
+ v.use_second(i) := kk(3);
+ v.byte_index(i) := kk(2 downto 0);
+ end loop;
+
+ for i in 0 to 7 loop
+ if i < to_integer(unsigned(v.length)) then
+ if v.dwords_done = '1' then
+ v.trim_ctl(i) := '1' & not v.use_second(i);
+ else
+ v.trim_ctl(i) := "10";
+ end if;
+ else
+ v.trim_ctl(i) := '0' & v.sign_extend;
+ end if;
+ end loop;
+
-- Update outputs to dcache
d_out.valid <= req and not v.align_intr;
d_out.load <= v.load;
-- Multiplex either cache data to the destination GPR or
-- the address for the rA update.
l_out.valid <= done;
- if r.mfspr = '1' then
+ case r.wr_sel is
+ when "00" =>
l_out.write_enable <= '1';
l_out.write_reg <= r.write_reg;
l_out.write_data <= r.sprval;
- elsif do_update = '1' then
- l_out.write_enable <= '1';
+ when "01" =>
+ l_out.write_enable <= do_update;
l_out.write_reg <= gpr_to_gspr(r.update_reg);
l_out.write_data <= r.addr;
- elsif lfs_done = '1' then
+ when "10" =>
l_out.write_enable <= '1';
l_out.write_reg <= r.write_reg;
l_out.write_data <= load_dp_data;
- else
+ when others =>
l_out.write_enable <= write_enable;
l_out.write_reg <= r.write_reg;
l_out.write_data <= data_trimmed;
- end if;
+ end case;
l_out.xerc <= r.xerc;
l_out.rc <= r.rc and done;
l_out.store_done <= d_in.store_done;
projects / microwatt.git / commitdiff