(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 92c657ecb2cc9824f445575d1e47dc0dab9362b9..6ef96a6cffe5e67ee68e974bebdaeee5a87fa58f 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -72,7 +72,7 @@ An autogenerator containing CSV files is available so that the task of creating
 
 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
 * power-gem5: TODO
-* TestIssuer: TIDO
+* TestIssuer: TODO
 * Microwatt: TODO
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
@@ -130,7 +130,7 @@ This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must b
 
 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 
-* ISACaller: TODO
+* ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 * power-gem5: TODO
 * TestIssuer: TODO
 * Microwatt: TODO