test single-cycle align phase on 64-bit add

diff --git a/src/add/test_add64.py b/src/add/test_add64.py
index c79771649699de4fc6143daf9c8766a83d125888..950897eaf235d476b525901e5c31eb12a8d02daa 100644 (file)
--- a/src/add/test_add64.py
+++ b/src/add/test_add64.py
@@ -85,6 +85,6 @@ def testbench(dut):
         #yield from check_case(dut, 1, 1, 1)
 
 if __name__ == '__main__':
-    dut = FPADD(width=64)
+    dut = FPADD(width=64, single_cycle=True)
     run_simulation(dut, testbench(dut), vcd_name="test_add64.vcd")