change to more well-known vector op names

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index a9a2fa4d8c251ad71e65238faf04770741175324..0bba849233d1d62a780b4d9f2db9e4e9be7e1692 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -147,10 +147,10 @@ CR based predication.  TODO: select alternate CR for twin predication? see [[dis
 This is a novel concept that allows predication to be applied to a single source and a single dest register.  The following types of traditional Vector operations may be encoded with it, *without requiring explicit opcodes to do so*
 
 * VSPLAT (a single scalar distributed across a vector)
-* VEXTRACT (a single scalar taken from a vector)
-* VINSERT (a scalar inserted into a vector)
-* VREDUCE (sequential selection of certain elements)
-* VEXPAND (insertion of a sequence of elements)
+* VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction))
+* VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction))
+* VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics))
+* VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics))
 
 Those patterns (and more) may be applied to:
 
@@ -163,7 +163,7 @@ Those patterns (and more) may be applied to:
 
 This is a huge list that creates extremely powerful combinations, particularly given that one of the predicate options is `(1<<r3)`
 
-Additional unusual capabilities of Twin Predication include a back-to-back version of VREDUCE-VEXPAND which is effectively the ability to do an ordered multiple VINSERT.
+Additional unusual capabilities of Twin Predication include a back-to-back version of VCOMPRESS-VEXPAND which is effectively the ability to do an ordered multiple VINSERT.
 
 ## Twin Predication
 

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 2d4c407a943c814ae66bc20c4816dffbc8938b2f..71e574e08b1e1196b8effd05722887e54bd17bc0 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -37,7 +37,7 @@ something like:
 
 ## twin predication, CR based.
 
-separate src and dest predicates are a critical part of SV for provision of VEXPAND, VREDUCE, VSPLAT, VINSERT and many more operations.
+separate src and dest predicates are a critical part of SV for provision of VEXPAND, VCOMPRESS, VSPLAT, VINSERT and many more operations.
 
 Twin CR predication could be done in two ways: