test top bit 31 in 32-bit mode for CR0 creation

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 5d5f0cb4f5382a816fcd7344e35508c0c8bbdae1..fb1310cad2c4ed92381d0bb64ea002673590387a 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -55,7 +55,10 @@ class CommonOutputStage(PipeModBase):
 
         comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
         comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
-        comb += msb_test.eq(target[-1] ^ is_cmp)
+        with m.If(op.is_32bit):
+            comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
+        with m.Else():
+            comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
         comb += is_nzero.eq(target.bool())
         comb += is_positive.eq(is_nzero & ~msb_test)
         comb += is_negative.eq(is_nzero & msb_test)

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 4b7fea86c7820775980a3943368aa637b8652b37..2814669c90446370e323bcefed4658491066fb5b 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -121,6 +121,14 @@ class DIVTestCase(FHDLTestCase):
         initial_regs[5] = 0x6b8aee2ccf7d62e9
         self.run_tst_program(Program(lst), initial_regs)
 
+    def test_6_regression(self):
+        # CR0 not getting set properly for this one
+        lst = ["divw. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x61c1cc3b80f2a6af
+        initial_regs[2] = 0x9dc66a7622c32bc0
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_rand_divw(self):
         insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):