cell mux naming convention (forgot to save, whoops)

diff --git a/src/wire_def.py b/src/wire_def.py
index aca972b3c5a7d9893e4b355801bceb9ea614b3f9..dd4b384ab9df1569c9b578650ae63f7460e84981 100644 (file)
--- a/src/wire_def.py
+++ b/src/wire_def.py
@@ -1,9 +1,9 @@
 # == Intermediate wire definitions ==#
 muxwire = '''
-      Wire#(Bit#({1}))   wrmux{0} <-mkDWire(0);'''
+      Wire#(Bit#({1}))   wrcell{0}_mux <-mkDWire(0);'''
 generic_io = '''
-      GenericIOType cell{0}_out=unpack(0);
-      Wire#(Bit#(1)) cell{0}_in <-mkDWire(0);
+      GenericIOType cell{0}_mux_out=unpack(0);
+      Wire#(Bit#(1)) cell{0}_mux_in <-mkDWire(0);
 '''
 uartwires = '''
       Wire#(Bit#(1)) wruart{0}_rx <-mkDWire(0);