add SPBlock_512W64B8W.v blackbox file

diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
index ab73b7bfa8573213d5497d5316565abb72c98d60..434bcda34c04791ad4408734af93c45fdd43d12f 100644 (file)
--- a/src/soc/litex/florent/Makefile
+++ b/src/soc/litex/florent/Makefile
@@ -10,6 +10,7 @@ ls180:
        yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'
        yosys -p 'read_verilog ls180.v' \
+             -p 'read_verilog SPBlock_512W64B8W.v' \
           -p 'write_ilang ls180_cvt.il'
        yosys -p 'read_ilang ls180_cvt.il' \
           -p 'read_ilang libresoc_cvt.il' \

diff --git a/src/soc/litex/florent/SPBlock_512W64B8W.v b/src/soc/litex/florent/SPBlock_512W64B8W.v
new file mode 100644 (file)
index 0000000..ddab968
--- /dev/null
+++ b/src/soc/litex/florent/SPBlock_512W64B8W.v
@@ -0,0 +1,7 @@
+(* blackbox = 1 *)
+module SPBlock_512W64B8W(input [8:0] a,
+                        input [63:0] d,
+                        output [63:0] q,
+                        input [7:0] we,
+                        input clk);
+endmodule // SPBlock_512W64B8W