(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 0b618f5ce3037d04d2fce3bf7d06c178fe1358ac..e89bf70c48d9d6365b9bf8c2d30a19bbc87dcef1 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -240,6 +240,21 @@ be suitably adapted to each category.
 * CR Field ops
 * Branch-Conditional - saves on instruction count in 3D parallel if/else
 
+It does have to be pointed out that there is huge pressure on the
+Mode bits.  There was therefore insufficient room, unlike the way that
+EXT001 was designed, to provide "identifying bits" *without first partially
+decoding the Suffix*.  This should in no way be conflated with or taken
+as an indicator that changing the meaning of the Suffix is performed
+or desirable.
+
+Some considerable care has been taken to ensure that Decoding may be
+performed in a strict forward-pipelined fashion that, aside from changes in
+SVSTATE and aside from the initial 32/64 length detection (also kept simple),
+a Multi-Issue Engine would have no difficulty (performance maximisable).
+With the initial partial RM identification
+decode performed above the Vector operations may easily be passed downstream
+to independent parallel units for further analysis.
+
 **Vectorised Branch-Conditional**
 
 As mentioned in the introduction this is the one sole instruction group