Added avail params to ilang format, check module params in 'hierarchy -check'
authorClifford Wolf <clifford@clifford.at>
Sat, 22 Oct 2016 09:05:49 +0000 (11:05 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 22 Oct 2016 09:05:49 +0000 (11:05 +0200)
backends/ilang/ilang_backend.cc
frontends/ast/ast.cc
frontends/ilang/ilang_parser.y
passes/hierarchy/hierarchy.cc

index 14e15017dbbc7275993f0bc43d893543d70d2bc6..16d1a97f537b080b6e73636587ccff0382aa05c2 100644 (file)
@@ -278,6 +278,13 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
                }
 
                f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
+
+               if (!module->avail_parameters.empty()) {
+                       if (only_selected)
+                               f << stringf("\n");
+                       for (auto &p : module->avail_parameters)
+                               f << stringf("%s" "  parameter %s\n", indent.c_str(), p.c_str());
+               }
        }
 
        if (print_body)
index fd27240090bd448a72c06903359cc69b11a16ca3..92513a2443ee247c491df5c7ceaaa4e92c57efd5 100644 (file)
@@ -934,10 +934,15 @@ static AstModule* process_module(AstNode *ast, bool defer)
                if (flag_lib) {
                        std::vector<AstNode*> new_children;
                        for (auto child : ast->children) {
-                               if (child->type == AST_WIRE && (child->is_input || child->is_output))
+                               if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
                                        new_children.push_back(child);
-                               else
+                               } else if (child->type == AST_PARAMETER) {
+                                       child->delete_children();
+                                       child->children.push_back(AstNode::mkconst_int(0, false, 0));
+                                       new_children.push_back(child);
+                               } else {
                                        delete child;
+                               }
                        }
                        ast->children.swap(new_children);
                        ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
index fe5f23d66ff9295aaae7b9dbf486e6413e189367..bfc062fec0f4fa0466edc89dbe42f1d9ade8da25 100644 (file)
@@ -112,7 +112,13 @@ module_body:
        /* empty */;
 
 module_stmt:
-       attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
+       param_stmt | attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
+
+param_stmt:
+       TOK_PARAMETER TOK_ID EOL {
+               current_module->avail_parameters.insert($2);
+               free($2);
+       };
 
 attr_stmt:
        TOK_ATTRIBUTE TOK_ID constant EOL {
index 4d1e3987bd67cffa823d1ee067567adb144d4066..9db407c7aac71ac4c04de51f3ae32422cef0c4d2 100644 (file)
@@ -212,6 +212,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
                                } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
                                        log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
                                                        log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
+                       for (auto &param : cell->parameters)
+                               if (mod->avail_parameters.count(param.first) == 0)
+                                       log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
+                                                       log_id(cell->type), log_id(module), log_id(cell), log_id(param.first));
                }
 
                if (cell->parameters.size() == 0)