add samuel to about us
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 9 Jul 2020 08:45:33 +0000 (09:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 9 Jul 2020 08:45:33 +0000 (09:45 +0100)
about_us.mdwn

index a1a29d84299b5c37a8d8d11a172b54c13650fe7f..9cd0815f1e4f2c26e20771b288ca188d682fa443 100644 (file)
@@ -119,3 +119,22 @@ Alain's website: <http://phcomp.co.uk>
 * Github Profile: [[https://github.com/Sanjay-A-Menon]]
 * LinkedIn Profile: [[https://www.linkedin.com/in/sanjay-menon-91791815a]]
 * Availability: ~6hrs/week
+
+## Samuel Falvo
+
+* Experience in amateur HDL projects (Kestrel-3 homebrew computer
+   concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB
+   design.  Extensive experience with test-driven development, Python, RISC-V
+   assembly language, and Forth.  Very comfortable with nMigen, but still
+   learning things.
+* Interests: Forth, Common Lisp, Scheme, assembly language,
+   {Astro|Semiconductor-}physics, astronomy, martial arts, furry
+* Websites:
+  - https://hackaday.io/project/170581-vdc-ii ,
+  - https://kestrelcomputer.github.io/kestrel/ ,
+  - http://chiselapp.com/user/kc5tja/repository/kestrel-3/index
+* Public Repositories:
+  - https://github.com/sam-falvo ,
+  - https://github.com/kestrelcomputer
+* Availability: approximately 20 hrs/wk, circumstances permitting.
+