add axi 32-bit reg fn

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 41d92402f7a8114e627aed0ef5cdb1b824c04b94..ab68dcbbe7cbae52da50d213aea0e99d4bb3d2cd 100644 (file)
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -10,6 +10,9 @@ class uart(PBase):
         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" \
                "            method Bit#(1) uart{0}_intr;"
 
+    def num_axi_regs32(self):
+        return 8
+
 
 class rs232(PBase):
     def importfn(self):
@@ -19,6 +22,9 @@ class rs232(PBase):
     def ifacedecl(self):
         return "            interface RS232 uart{0}_coe;"
 
+    def num_axi_regs32(self):
+        return 2
+
 
 class twi(PBase):
     def importfn(self):
@@ -28,6 +34,9 @@ class twi(PBase):
         return "            interface I2C_out i2c{0}_out;\n" \
                "            method Bit#(1) i2c{0}_isint;"
 
+    def num_axi_regs32(self):
+        return 8
+
 
 class qspi(PBase):
     def importfn(self):
@@ -37,6 +46,9 @@ class qspi(PBase):
         return "            interface QSPI_out qspi{0}_out;\n" \
                "            method Bit#(1) qspi{0}_isint;"
 
+    def num_axi_regs32(self):
+        return 13
+
 
 class pwm(PBase):
     def importfn(self):
@@ -45,6 +57,9 @@ class pwm(PBase):
     def ifacedecl(self):
         return "        interface PWMIO pwm_o;"
 
+    def num_axi_regs32(self):
+        return 4
+
 
 class gpio(PBase):
     def importfn(self):
@@ -55,6 +70,9 @@ class gpio(PBase):
     def ifacedecl(self):
         return "        interface GPIO_config#({1}) pad_config{0};"
 
+    def num_axi_regs32(self):
+        return 2
+
 
 class PFactory(object):
     def getcls(self, name):