WIP adding ternlogi to ls007

diff --git a/openpower/sv/rfc/ls007.mdwn b/openpower/sv/rfc/ls007.mdwn
index 0c5e6bb0593785dfed68806f935670195228a2d1..2102fb90b9b11aec38888e1317cfad3c10e625b1 100644 (file)
--- a/openpower/sv/rfc/ls007.mdwn
+++ b/openpower/sv/rfc/ls007.mdwn
@@ -15,25 +15,25 @@
 
 **Target**: v3.2B
 
-**Source**: v3.0B
+**Source**: v3.1B
 
 **Books and Section affected**: **UPDATE**
 
-```
-    Book I 64-bit Fixed-Point Arithmetic Instructions 3.3.9.1
-    Appendix E Power ISA sorted by opcode
-    Appendix F Power ISA sorted by version
-    Appendix G Power ISA sorted by Compliancy Subset
-    Appendix H Power ISA sorted by mnemonic
-```
+* Book I 2.5.1 Condition Register Logical Instructions
+* Book I 3.3.13 Fixed-Point Logical Instructions
+* Appendix E Power ISA sorted by opcode
+* Appendix F Power ISA sorted by version
+* Appendix G Power ISA sorted by Compliancy Subset
+* Appendix H Power ISA sorted by mnemonic
 
 **Summary**
 
 Instructions added
 
-```
-    todo
-```
+* `ternlogi` -- Ternary Logic Immediate
+* `crternlogi` -- Condition Register Ternary Logic Immediate
+* `binlog` -- Dynamic Binary Logic
+* `crbinlog` -- Condition Register Dynamic Binary Logic
 
 **Submitter**: Luke Leighton (Libre-SOC)
 
@@ -41,42 +41,124 @@ Instructions added
 
 **Impact on processor**:
 
-```
-    Addition of two new GPR-based instructions
-    Addition of two new CR-field-based instructions
-```
+* Addition of two new GPR-based instructions
+* Addition of two new CR-field-based instructions
 
 **Impact on software**:
 
-```
-    Requires support for new instructions in assembler, debuggers,
-    and related tools.
-```
+* Requires support for new instructions in assembler, debuggers,
+  and related tools.
 
 **Keywords**:
 
 ```
-    GPR, CR-Field, bitmanipulation, ternary, binary
+GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table
 ```
 
 **Motivation**
 
+* `ternlogi` is similar to existing `and`/`or`/`xor`/etc. instructions, but
+  allows any arbitrary 3-input 1-output bitwise operation. This can be used to
+  combine several instructions into one. E.g. `A ^ (~B & (C | A))` can become
+  one instruction. This can also be used to have one instruction for
+  bitwise MUX `(A & B) | (~A & C)`.
+* `binlog` is like `ternlogi` except it supports any arbitrary 2-input
+  1-output bitwise operation, where the operation can be selected dynamically
+  at runtime. This operates similarly to LUTs in a FPGA.
+* `crternlogi` is like `ternlogi` except it works with CRs instead of GPRs.
+* `crbinlog` is like `binlog` except it works with CRs instead of GPRs.
 
 **Notes and Observations**:
 
+* `ternlogi` is like the existing `xxeval` instruction, except operates on
+  GPRs instead of VSRs and doesn't require VSX/VMX.
+* TODO: should we use imm7 instead of imm8 for `ternlogi`? This wouldn't make the decoder significantly more complex, since the immediate doesn't affect wether or not the instruction is defined. <https://libre-soc.org/openpower/sv/bitmanip/ternlogi_simplification_experiment/>
 
 **Changes**
 
 Add the following entries to:
 
-* the Appendices of Book I
-* Instructions of Book I added to Section 3.3.9.1
-* VA2-Form of Book I Section 1.6.21.1 and 1.6.2
+* Book I 2.5.1 Condition Register Logical Instructions
+* Book I 3.3.13 Fixed-Point Logical Instructions
+* Book I 1.6.1 and 1.6.2
 
 ----------------
 
 \newpage{}
 
+# CRB-FORM
+
+Add the following section to Book I 1.6.1
+
+```
+|0   |6   |9    |12   |15   |18   |21   |29  |31   |
+| PO | BF | BFA | BFB | BFC | msk | TLI | XO | msk |
+```
+
+# TLI-FORM
+
+Add the following section to Book I 1.6.1
+
+```
+|0   |6   |11  |16  |21   |29  |31  |
+| PO | RT | RA | RB | TLI | XO | Rc |
+```
+
+# Word Instruction Fields
+
+Add the following to Book I 1.6.2
+
+```
+msk (18:20, 31)
+    Field used by crternlogi to decide which CR bits to modify.
+    Formats: CRB
+```
+
+```
+TLI (21:28)
+    Field used by the ternlogi instruction as the
+    look-up table.
+    Formats: TLI, CRB
+```
+
+```
+XO (29:30)
+    Extended opcode field.
+    Formats: TLI, CRB
+```
+
+Add `TLI` to the `Formats:` list of all of `RA`, `RB`, `RT`, and `Rc`.
+Add `CRB` to the `Formats:` list of all of `BF`, `BFA`, `BFB`, and `BFC`.
+
+# Ternary Logic Immediate TLI-form
+
+* `ternlogi RT, RA, RB, TLI` (`Rc=0`)
+* `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
+
+| 0-5 | 6-10 | 11-15 | 16-20 | 21-28 | 29-30 | 31 | Form     |
+|-----|------|-------|-------|-------|-------|----|----------|
+| PO  | RT   |  RA   |  RB   | TLI   | XO    | Rc | TLI-Form |
+
+Pseudocode:
+
+```
+result <- [0] * 64
+do i = 0 to 63
+    idx <- (RT)[i] || (RA)[i] || (RB)[i]  # compute index from current bits
+    result[i] <- TLI[7 - idx]  # subtract from 7 to index in LSB0 order
+RT <- result
+```
+
+Special registers altered:
+
+```
+CR0                    (if Rc=1)
+```
+
+----------
+
+\newpage{}
+
 
 ----------
 
@@ -89,7 +171,7 @@ Add the following entries to:
 
 |Form| Book | Page | Version | mnemonic | Description |
 |----|------|------|---------|----------|-------------|
-|VA  | I    | #    | 3.2B    |todo   | |
+|TLI | I    | #    | 3.2B    | ternlogi | Ternary Logic Immediate |
 
 ----------------