(no commit message)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index b7b8e4ee840bcf68543611163e114fcad599bf0f..5d33915238bfa1d837215d1bea34ea1bc7bb8ac4 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -206,3 +206,13 @@ Note that:
   LSB of each element in the result vector
 
 Note that element width overrides are respected on the INT src or destination register (but that elwidth overrides on CRs are meaningless)
+
+# v3.1 setbc instructions
+
+there are additional setb conditional instructions in v3.1 (p129)
+
+    RT = (CR[BI] == 1) ? 1 : 0
+
+which also negate that, and also return -1 / 0.  these are similar yo crweird but not the same purpose.
+
+