fill in FPSCR bits modified by int <-> fp conversions

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index f363debb5ffb3c1a9d5928fd50863d4fc625160c..5a8d198a9a3d6e4d35c943b508cffaaf702663e2 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -467,8 +467,8 @@ operations.
 Special Registers altered:
 
 ```
-    CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?) (if IT[0]=1)
+    CR1               (if Rc=1)
+    FPRF FR FI FX XX  (if IT[0]=1)
 ```
 
 ### Assembly Aliases
@@ -529,7 +529,7 @@ Special Registers altered:
 
 ```
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?)
+    FPRF FR FI FX XX
 ```
 
 ### Assembly Aliases
@@ -805,7 +805,7 @@ Special Registers altered:
 ```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
-    FPCSR   (TODO: which bits?)
+    FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
 ```
 
 ### Assembly Aliases
@@ -953,7 +953,7 @@ Special Registers altered:
 ```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
-    FPCSR   (TODO: which bits?)
+    FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
 ```
 
 ### Assembly Aliases

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 8cc92d775c7cc1d76825ad9bf354fe73ddbc6c95..e7c616ec925ccc5faeec2f3711230edee5ff0f5b 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -314,8 +314,8 @@ operations.
 Special Registers altered:
 
 ```
-    CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?) (if IT[0]=1)
+    CR1               (if Rc=1)
+    FPRF FR FI FX XX  (if IT[0]=1)
 ```
 
 ### Assembly Aliases
@@ -380,7 +380,7 @@ Special Registers altered:
 
 ```
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?)
+    FPRF FR FI FX XX
 ```
 
 ### Assembly Aliases
@@ -668,7 +668,7 @@ Special Registers altered:
 ```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
-    FPCSR   (TODO: which bits?)
+    FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
 ```
 
 ### Assembly Aliases
@@ -820,7 +820,7 @@ Special Registers altered:
 ```
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
-    FPCSR   (TODO: which bits?)
+    FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
 ```
 
 ### Assembly Aliases