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diff --git a/3d_gpu/architecture/inorder_model.mdwn b/3d_gpu/architecture/inorder_model.mdwn
index 93318305ce7e153cfca0f59611d0c4e014f97e40..b0679dc0c2f720c25a860d47cc1bea28a417d9c9 100644 (file)
--- a/3d_gpu/architecture/inorder_model.mdwn
+++ b/3d_gpu/architecture/inorder_model.mdwn
@@ -3,19 +3,21 @@
 * First steps for a newbie developer [[docs/firststeps]]
 * bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=1039>
 
-At present *[Update when this is no longer the case]*, the Libre-SOC core
+The Libre-SOC TestIssuer core
 utilises a Finite-State Machine (FSM) to control the fetch/dec/issue/exec
 pipelines, with only one pipeline being active at any given time. This is good
 for debugging the HDL, but severly restricts performance as a single
-instruction will take tens of clock cycles to complete.
+instruction will take tens of clock cycles to complete.  In-development
+(Andrey to research and link to the relevant bugreport) is an in-order
+core and following on from that will be an out-of-order core.
 
 A Single-Issue In-Order control unit will allow every pipepline to be active,
 and raises the ideal maximum throughput to 1 instruction per clock cycle,
 bearing any register hazards.
 
-This control unit has not been written in HDL yet, however there's currently a
+This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/), however there's currently a
 task to develop the model for the simulator first. The model will be used to
-determine performance (and eventually to write the HDL).
+determine performance.
 
 Diagram that Luke drew comparing pipelines and fsms: