Properly wire core reset to ti_rst

This partially fixes Bug #812

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index a80941dbd26e01ff6cc014cb1fab1531ff509fda..e41a844c2e2a8eec9869ff480a9bb6428c5992fe 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -457,13 +457,12 @@ class TestIssuerBase(Elaboratable):
         comb += cd_por.clk.eq(ClockSignal())
 
         # power-on reset delay
-        core_rst = ResetSignal(self.core_domain)
         if self.core_domain != "sync":
             comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
-            comb += core_rst.eq(ti_rst)
+            comb += self.core_rst.eq(ti_rst)
         else:
             with m.If(delay != 0 | dbg.core_rst_o):
-                comb += core_rst.eq(1)
+                comb += self.core_rst.eq(1)
         with m.If(stop_delay != 0):
             # run DMI core-stop as well but on an extra couple of cycles
             comb += dbg.core_stopped_i.eq(1)